dac1005d650 NXP Semiconductors, dac1005d650 Datasheet - Page 12

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dac1005d650

Manufacturer Part Number
dac1005d650
Description
Dual 10-bit Dac, Up To 650 Msps; 2? 4? And 8? Interpolating
Manufacturer
NXP Semiconductors
Datasheet

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Part Number
Manufacturer
Quantity
Price
Part Number:
dac1005d650HW/C1,5
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
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Part Number:
dac1005d650HW/C1:5
Manufacturer:
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Quantity:
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NXP Semiconductors
Table 5.
V
T
unless otherwise specified.
[1]
[2]
[3]
[4]
DAC1005D650_1
Product data sheet
Symbol
SFDR
IMD3
ACPR
NSD
amb
DDA(1V8)
D = guaranteed by design; C = guaranteed by characterization; I = 100 % industrially tested.
CLKP and CLKN inputs are at differential LVDS levels. An external differential resistor with a value of between 80
be connected across the pins (see
and the inductance between the receiver and the driver circuit ground.
IMD3 rejection with 6 dBFS/tone.
V
= 40 C to +85 C; typical values measured at T
gpd
RBW
represents the ground potential difference voltage. This is the voltage that results from current flowing through the finite resistance
= V
Characteristics
DDD(1V8)
Parameter
restricted bandwidth
spurious-free dynamic
range
third-order
intermodulation
distortion
adjacent channel
power ratio
noise spectral density
= 1.8 V; V
…continued
DDA(3V3)
Figure
= V
Conditions
f
0 dBFS
f
f
Msps; f
f
Msps; f
f
Msps; f
f
f
s
f
s
data
data
data
s
o
s
8).
= 640 Msps; f
= 640 Msps; 8 interpolation
= 640 Msps; 8 interpolation;
= 19 MHz at 0 dBFS
2.51 MHz f
B = 30 kHz
2.71 MHz f
B = 30 kHz
3.51 MHz
B = 30 kHz
4 MHz
B = 1 MHz
f
f
f
f
1 carrier; B = 5 MHz
2 carriers; B = 10 MHz
4 carriers; B = 20 MHz
1 carrier; B = 5 MHz
2 carriers; B = 10 MHz
4 carriers; B = 20 MHz
1 carrier; B = 5 MHz
2 carriers; B = 10 MHz
4 carriers; B = 20 MHz
noise shaper disabled
noise shaper enabled
= 320 Msps; 4 interpolation
o1
o1
o1
o1
DD(IO)(3V3)
= 76.8 MHz; f
= 153.6 MHz; f
= 153.6 MHz; f
= 49 MHz; f
= 95 MHz; f
= 95 MHz; f
= 152 MHz; f
o
o
o
= 96 MHz
= 115.2 MHz
= 153.6 MHz
Rev. 01 — 28 July 2009
f
offset
= 3.3 V; AGND, DGND and GNDIO shorted together;
Dual 10-bit DAC, up to 650 Msps; 2 4 and 8 interpolating
amb
f
offset
offset
offset
o
o2
o2
o2
= 96 MHz at
= 25 C; R
s
o2
40 MHz;
s
s
= 51 MHz
= 97 MHz
= 97 MHz
= 614.4
= 154 MHz C
= 614.4
= 614.4
2.71 MHz;
3.51 MHz;
4 MHz;
L
= 50 ; I
Test
I
I
I
I
C
C
I
I
C
C
C
C
C
C
C
C
C
C
[1]
O(fs)
[4]
[4]
[4]
[4]
= 20 mA; maximum sample rate; PLL on;
Min
-
-
-
-
-
-
67
-
-
-
-
-
-
-
-
-
-
-
-
DAC1005D650
Typ
81
80
79
77
64
61
60
67
63
60
65
63
60
89
88
89
83
138 -
139 -
Max
-
-
-
-
-
-
-
-
-
-
-
-
-
-
83
81
67
© NXP B.V. 2009. All rights reserved.
and 120
Unit
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dB
dB
dB
dB
dB
dB
dB
dB
dB
dBm/Hz
dBm/Hz
12 of 41
should

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