dac1005d650 NXP Semiconductors, dac1005d650 Datasheet - Page 24

• Manufacturer Part Number: dac1005d650
• Description: Dual 10-bit Dac, Up To 650 Msps; 2? 4? And 8? Interpolating
• Manufacturer: NXP Semiconductors

NXP Semiconductors
DAC1005D650_1
Product data sheet
Table 31.
The settings applied to PLL_PHASE[1:0] (register 02h[2:1]) and PLL_POL
(register 02h[0]), allows adjustment of the phase and polarity of the sampling clock. This
occurs at the input of the DAC core and depends mainly on the sampling frequency. Some
examples are given in
Table 32.
Mode
Dual-port
Dual-port
Dual-port
Interleaved
Interleaved
Interleaved
Mode
Dual-port
Dual-port
Dual-port
Interleaved
Interleaved
Interleaved
Frequencies
Sample clock phase and polarity examples
CLK input
(MHz)
160
160
80
320
320
160
Input data rate
(MHz)
80
80
80
160
160
160
Table 32 “Sample clock phase and polarity
Rev. 01 — 28 July 2009
Dual 10-bit DAC, up to 650 Msps; 2 4 and 8 interpolating
Input data rate
(MHz)
160
160
80
320
320
160
Interpolation
2
4
8
2
4
8
Interpolation
2
4
8
2
4
8
Update rate
(Msps)
160
320
640
160
320
640
DAC1005D650
Update rate
(Msps)
320
640
640
320
640
640
PLL_PHASE
[1:0]
01
01
01
01
01
01
examples”.
© NXP B.V. 2009. All rights reserved.
PLL_DIV[1:0]
01 (/4)
01 (/4)
10 (/8)
00 (/2)
00 (/2)
01 (/4)
PLL_POL
1
0
1
1
0
1
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