dac1005d650 NXP Semiconductors, dac1005d650 Datasheet - Page 23

• Manufacturer Part Number: dac1005d650
• Description: Dual 10-bit Dac, Up To 650 Msps; 2? 4? And 8? Interpolating
• Manufacturer: NXP Semiconductors

NXP Semiconductors
DAC1005D650_1
Product data sheet
10.5 Timing
The DAC1005D650 can operate at an update rate (f
data rate (f
diagram”.
The typical performances are measured at 50 % duty cycle but any timing within the limits
of the characteristics will not alter the performance.
In
The setting applied to PLL_DIV[1:0] (register 02h[4:3]; see
(address 02h) bit
core to be adjusted.
Fig 8.
Fig 9.
Fig 10. Input timing diagram
Table 31
(CLKP-CLKN)
LVDS clock configuration
Interfacing CML to LVDS
n in Qn = 0 to 9 and for In is 0 to 9.
data
“Frequencies”, the links between internal and external clocking are defined.
In/Qn
CLK
) of up to 160 MHz. The input timing is shown in
description”) allows the frequency between the digital part and the DAC
CML
Rev. 01 — 28 July 2009
Z = 50
Z = 50
Dual 10-bit DAC, up to 650 Msps; 2 4 and 8 interpolating
90 %
LVDS
t
su(i)
Z = 50
Z = 50
Zdiff =
100
100 nF
100 nF
N
50 %
V
DDA(1V8)
AGND
t
h(i)
90 %
1.1 k
2.2 k
Zdiff =
100
CLKN
CLKP
55
55
100 nF
CLKP
CLKN
s
) of up to 650 Msps and with an input
N + 1
001aah021
t
w(CLK)
LVDS
Table 12 “PLLCFG register
DAC1005D650
001aah020
Figure 10 “Input timing
LVDS
N + 2
© NXP B.V. 2009. All rights reserved.
001aaj815
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