dac1005d650 NXP Semiconductors, dac1005d650 Datasheet - Page 14

• Manufacturer Part Number: dac1005d650
• Description: Dual 10-bit Dac, Up To 650 Msps; 2? 4? And 8? Interpolating
• Manufacturer: NXP Semiconductors

NXP Semiconductors
DAC1005D650_1
Product data sheet
Fig 3.
RESET_N
(optional)
(optional)
SCS_N
SCLK
SDIO
SDO
R/W indicates the mode access (see
SPI protocol
10.2.2 SPI timing description
R/W
Table 6.
In
Table 7.
A0 to A4 indicates which register is being addressed. In the case of a multiple transfer,
this address concerns the first register after which the next registers follow directly in
decreasing order according to
SPI can operate at a frequency of up to 15 MHz. The SPI timing is shown in
R/W
0
1
N1
0
0
1
1
N1
Fig 4.
Table 7
RESET_N
(optional)
N0
SCS_N
SCLK
SDIO
SPI timing diagram
N1 and N0 indicate the number of bytes transferred after the instruction byte.
Read or Write mode access description
Number of bytes to be transferred
A4
Table
A3
Description
Write mode operation
Read mode operation
50 %
50 %
N0
0
1
0
1
50 %
6).
A2
t
w(RESET_N)
Rev. 01 — 28 July 2009
50 %
Dual 10-bit DAC, up to 650 Msps; 2 4 and 8 interpolating
A1
Table 9 “Register allocation
t
t
su(SCS_N)
su(SDIO)
A0
t
h(SDIO)
D7
D7
Number of bytes
1 byte transferred
2 bytes transferred
3 bytes transferred
4 bytes transferred
D6
D6
D5
D5
t
w(SCLK)
D4
D4
map”.
DAC1005D650
D3
D3
D2
D2
© NXP B.V. 2009. All rights reserved.
D1
D1
Figure
D0
D0
t
h(SCS_N)
001aaj813
001aaj812
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4.