mt48lc16m16a2tg-7e-it Micron Semiconductor Products, mt48lc16m16a2tg-7e-it Datasheet - Page 70

• Manufacturer Part Number: mt48lc16m16a2tg-7e-it
• Description: 256mb X4, X8, X16 Sdram
• Manufacturer: Micron Semiconductor Products

Figure 50:
PDF: 09005aef8091e6d1/Source: 09005aef8091e6a8
256MSDRAM_2.fm - Rev. L 10/07 EN
DQML, DQMU
COMMAND
A0–A9, A11
BA0, BA1
DQM/
CLK
CKE
A10
DQ
t CMS
t CKS
t AS
t AS
t AS
Single Write – Without Auto Precharge
ACTIVE
T0
ROW
ROW
BANK
t CKH
t CMH
Notes:
t AH
t AH
t AH
t RCD
t RAS
t RC
t CK
T1
1. For this example, BL = 1, and the WRITE burst is followed by a “manual” PRECHARGE.
2. 14ns to 15ns is required between <D
3. x16: A8, A9, and A11 = “Don’t Care”
4. PRECHARGE command not allowed (would violate
NOP
quency. With a single WRITE,
requirement.
x8: A9 and A11 = “Don’t Care”
x4: A11 = “Don’t Care”
DISABLE AUTO PRECHARGE
t CMS
t CL
t DS
COLUMN m 3
WRITE
T2
BANK
D
IN
t CMH
t CH
t DH
m
t WR
4
NOP 2
T3
70
t
WR has been increased to meet minimum
NOP 2
T4
IN
m> and the PRECHARGE command, regardless of fre-
Micron Technology, Inc., reserves the right to change products or specifications without notice.
SINGLE BANK
PRECHARGE
ALL BANKS
T5
BANK
t
RAS).
t RP
256Mb: x4, x8, x16 SDRAM
NOP
T6
©1999 Micron Technology, Inc. All rights reserved.
ACTIVE
BANK
ROW
T7
Timing Diagrams
t
RAS
NOP
T8
DON’T CARE