mt48lc16m16a2tg-7e-it Micron Semiconductor Products, mt48lc16m16a2tg-7e-it Datasheet - Page 41

• Manufacturer Part Number: mt48lc16m16a2tg-7e-it
• Description: 256mb X4, X8, X16 Sdram
• Manufacturer: Micron Semiconductor Products

Table 9:
PDF: 09005aef8091e6d1/Source: 09005aef8091e6a8
256MSDRAM_2.fm - Rev. L 10/07 EN
CKE
H
H
L
L
n - 1
CKE
H
H
Truth Table 2 – CKE
Notes 1–4 apply to the entire table
L
L
n
Notes:
Reading or writing
Current State
Clock suspend
Clock suspend
All banks idle
All banks idle
Power-down
Power-down
1. CKE
2. Current state is the state of the SDRAM immediately prior to clock edge n.
3. Command
4. All states and sequences not shown are illegal or reserved.
5. Exiting power-down at clock edge n will put the device in the all banks idle state in time for
6. Exiting self refresh at clock edge n will put the device in the all banks idle state after
7. After exiting clock suspend at clock edge n, the device will resume operation and recognize
Self refresh
Self refresh
clock edge.
Command
clock edge n + 1 (provided that
met. COMMAND INHIBIT or NOP commands should be issued on any clock edges occurring
during the
period.
the next command at clock edge n + 1.
n
is the logic state of CKE at clock edge n; CKE
n
n
t
.
is the command registered at clock edge n, and Action
XSR period. A minimum of two NOP commands must be provided during
COMMAND INHIBIT or NOP
COMMAND INHIBIT or NOP
COMMAND INHIBIT or NOP
See Table 10 on page 42
AUTO REFRESH
WRITE or NOP
Command
41
t
CKS is met).
X
X
X
X
Micron Technology, Inc., reserves the right to change products or specifications without notice.
n
n - 1
256Mb: x4, x8, x16 SDRAM
was the state of CKE at the previous
Maintain clock suspend
Maintain power-down
Maintain self refresh
Clock suspend entry
Power-down entry
Exit clock suspend
Exit power-down
Self refresh entry
Exit self refresh
Action
©1999 Micron Technology, Inc. All rights reserved.
n
is a result of
n
Operations
Notes
t
XSR is
t
5
6
7
XSR