mt48lc16m16a2tg-7e-it Micron Semiconductor Products, mt48lc16m16a2tg-7e-it Datasheet - Page 63

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mt48lc16m16a2tg-7e-it

Manufacturer Part Number
mt48lc16m16a2tg-7e-it
Description
256mb X4, X8, X16 Sdram
Manufacturer
Micron Semiconductor Products
Datasheet
Figure 43:
PDF: 09005aef8091e6d1/Source: 09005aef8091e6a8
256MSDRAM_2.fm - Rev. L 10/07 EN
DQML, DQMU
COMMAND
BA0, BA1
A11,A12
A0–A9,
DQM/
CKE
A10
CLK
DQ
t CMS
t CKS
t AS
t AS
t AS
Single Read – Without Auto Precharge
ACTIVE
ROW
ROW
BANK
T0
t CMH
t CKH
t AH
t AH
t AH
Notes:
t RCD
t RAS
t RC
t CK
T1
NOP
1. For this example, BL = 1, CL = 2, and the READ burst is followed by a “manual” PRECHARGE.
2. PRECHARGE command not allowed (would violate
3. x16: A9, A11, and A12 = “Don’t Care”
x8: A11 and A12 = “Don’t Care”
x4: A12 = “Don’t Care”
DISABLE AUTO PRECHARGE
t CMS
t CL
COLUMN m
BANK
T2
READ
t CMH
t CH
CAS Latency
3
T3
NOP
t LZ
2
t AC
63
D
T4
NOP
OUT
t OH
t HZ
2
m
Micron Technology, Inc., reserves the right to change products or specifications without notice.
SINGLE BANKS
PRECHARGE
ALL BANKS
BANK(S)
T5
t RP
t
RAS).
T6
256Mb: x4, x8, x16 SDRAM
NOP
©1999 Micron Technology, Inc. All rights reserved.
ACTIVE
ROW
BANK
T7
ROW
Timing Diagrams
T8
NOP
DON’T CARE
UNDEFINED

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