mt48lc16m16a2tg-7e-it Micron Semiconductor Products, mt48lc16m16a2tg-7e-it Datasheet - Page 24

• Manufacturer Part Number: mt48lc16m16a2tg-7e-it
• Description: 256mb X4, X8, X16 Sdram
• Manufacturer: Micron Semiconductor Products

Auto Precharge
BURST TERMINATE
Figure 9:
AUTO REFRESH
PDF: 09005aef8091e6d1/Source: 09005aef8091e6a8
256MSDRAM_2.fm - Rev. L 10/07 EN
Terminating a WRITE Burst
Note:
Auto precharge is a feature that performs the same individual-bank precharge function
described above, without requiring an explicit command. This is accomplished by using
A10 to enable auto precharge in conjunction with a specific READ or WRITE command.
A precharge of the bank/row that is addressed with the READ or WRITE command is
automatically performed upon completion of the READ or WRITE burst, except in the
full-page burst mode, where auto precharge does not apply. Auto precharge is nonper-
sistent in that it is either enabled or disabled for each individual READ or WRITE
command.
Auto precharge ensures that the precharge is initiated at the earliest valid stage within a
burst. The user must not issue another command to the same bank until the precharge
time (
issued at the earliest possible time, as described for each burst type in “Operations” on
page 25.
The BURST TERMINATE command is used to truncate either fixed-length or full-page
bursts. The most recently registered READ or WRITE command prior to the BURST
TERMINATE command will be truncated, as shown in “Operations” on page 25. The
BURST TERMINATE command does not precharge the row; the row will remain open
until a PRECHARGE command is issued.
COMMAND
AUTO REFRESH is used during normal operation of the SDRAM and is analogous to
CAS#-BEFORE-RAS# (CBR) refresh in conventional DRAMs. This command is nonper-
sistent, so it must be issued each time a refresh is required. All active banks must be
precharged prior to issuing an AUTO REFRESH command. The AUTO REFRESH
command should not be issued until the minimum
PRECHARGE command, as shown in “Operations” on page 25.
The addressing is generated by the internal refresh controller. This makes the address
bits a “Don’t Care” during an AUTO REFRESH command. The 256Mb SDRAM requires
8,192 AUTO REFRESH cycles every 64ms (
ADDRESS
DQM is LOW.
t
CLK
DQ
RP) is completed. This is determined as if an explicit PRECHARGE command was
TRANSITIONING DATA
BANK,
WRITE
COL n
D
T0
n
IN
TERMINATE
BURST
T1
COMMAND
(ADDRESS)
DON’T CARE
(DATA)
NEXT
T2
24
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t
REF), regardless of width option. Providing a
t
RP has been met after the
256Mb: x4, x8, x16 SDRAM
©1999 Micron Technology, Inc. All rights reserved.
Commands