mt48lc16m16a2tg-7e-it Micron Semiconductor Products, mt48lc16m16a2tg-7e-it Datasheet - Page 32

• Manufacturer Part Number: mt48lc16m16a2tg-7e-it
• Description: 256mb X4, X8, X16 Sdram
• Manufacturer: Micron Semiconductor Products

Figure 18:
WRITEs
PDF: 09005aef8091e6d1/Source: 09005aef8091e6a8
256MSDRAM_2.fm - Rev. L 10/07 EN
Terminating a READ Burst
Note:
COMMAND
WRITE bursts are initiated with a WRITE command, as shown in Figure 19 on page 33.
The starting column and bank addresses are provided with the WRITE command, and
auto precharge is either enabled or disabled for that access. If auto precharge is enabled,
the row being accessed is precharged at the completion of the burst. For the generic
WRITE commands used in the following illustrations, auto precharge is disabled.
During WRITE bursts, the first valid data-in element will be registered coincident with
the WRITE command. Subsequent data elements will be registered on each successive
positive clock edge. Upon completion of a fixed-length burst, assuming no other
commands have been initiated, the DQs will remain High-Z, and any additional input
data will be ignored (see Figure 20 on page 33). A full-page burst will continue until
terminated. (At the end of the page, it will wrap to the start address and continue.)
COMMAND
ADDRESS
ADDRESS
DQM is LOW.
CLK
CLK
DQ
DQ
BANK,
T0
COL n
T0
BANK,
COL n
READ
READ
CL = 2
T1
T1
NOP
NOP
CL = 3
T2
T2
NOP
NOP
32
D
OUT
n
T3
T3
NOP
NOP
n + 1
D
D
OUT
OUT
n
Micron Technology, Inc., reserves the right to change products or specifications without notice.
TRANSITIONING DATA
TERMINATE
TERMINATE
T4
BURST
T4
BURST
X = 1 cycle
n + 2
D
n + 1
D
OUT
OUT
X = 2 cycles
T5
T5
NOP
NOP
256Mb: x4, x8, x16 SDRAM
n + 3
n + 2
D
D
OUT
OUT
T6
T6
NOP
NOP
n + 3
D
OUT
©1999 Micron Technology, Inc. All rights reserved.
DON’T CARE
T7
NOP
Operations