mt48lc16m16a2tg-7e-it Micron Semiconductor Products, mt48lc16m16a2tg-7e-it Datasheet - Page 35

• Manufacturer Part Number: mt48lc16m16a2tg-7e-it
• Description: 256mb X4, X8, X16 Sdram
• Manufacturer: Micron Semiconductor Products

Figure 24:
PDF: 09005aef8091e6d1/Source: 09005aef8091e6a8
256MSDRAM_2.fm - Rev. L 10/07 EN
WRITE-to-PRECHARGE
Note:
which the last desired input data element is registered. The auto precharge mode
requires a
truncating a WRITE burst, the DQM signal must be used to mask input data for the clock
edge prior to, and the clock edge coincident with, the PRECHARGE command. An
example is shown in Figure 24. Data n + 1 is either the last of a burst of two or the last
desired of a longer burst. Following the PRECHARGE command, a subsequent
command to the same bank cannot be issued until
coincident with the second clock (see Figure 24).
In the case of a fixed-length burst being executed to completion, a PRECHARGE
command issued at the optimum time (as described above) provides the same operation
that would result from the same fixed-length burst with auto precharge. The disadvan-
tage of the PRECHARGE command is that it requires that the command and address
buses be available at the appropriate time to issue the command; the advantage of the
PRECHARGE command is that it can be used to truncate fixed-length or full-page bursts.
Fixed-length or full-page WRITE bursts can be truncated with the BURST TERMINATE
command. When truncating a WRITE burst, the input data applied coincident with the
BURST TERMINATE command will be ignored. The last data written (provided that
DQM is LOW at that time) will be the input data applied one clock previous to the
BURST TERMINATE command. This is shown in Figure 9 on page 24, where data n is the
last desired data element of a longer burst.
COMMAND
COMMAND
t WR @ t CLK ≥ 15ns
t WR = t CLK < 15ns
ADDRESS
ADDRESS
DQM could remain LOW in this example if the WRITE burst is a fixed length of two.
DQM
DQM
CLK
DQ
DQ
t
WR of at least one clock plus time, regardless of frequency. In addition, when
BANK a,
BANK a,
WRITE
WRITE
COL n
COL n
D
D
T0
n
n
IN
IN
n + 1
n + 1
NOP
NOP
T1
D
D
IN
IN
t
WR
PRECHARGE
(a or all)
BANK
NOP
T2
35
t
WR
PRECHARGE
TRANSITIONING DATA
(a or all)
BANK
T3
NOP
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t RP
NOP
NOP
T4
t RP
BANK a,
t
ACTIVE
RP is met. The PRECHARGE is issued
ROW
NOP
T5
256Mb: x4, x8, x16 SDRAM
DON’T CARE
BANK a,
ACTIVE
ROW
NOP
T6
©1999 Micron Technology, Inc. All rights reserved.
Operations