mg84fl54 Megawin Technology, mg84fl54 Datasheet - Page 12

• Manufacturer Part Number: mg84fl54
• Description: Full-speed Usb Micro-controller
• Manufacturer: Megawin Technology

SB:
LOCK:
WDSFWP:
HWWIDL:
When HWENW is enabled, the content of HWWIDL will be loaded to WIDL in WDTCR register during power-up.
HWPS[2:0]:
When HWENW is enabled, the content of HWPS[2:0] will be load to PS[2:0] in WDTCR register during power-
up.
When power up, hardware will automatically do the following actions into WDTCR register as shown in Fig 4-1 if
HWENW is enable:
For example: If HWWIDL and HWPS[2:0] are programmed to be 1 and 5, respectively, then WDTCR will be
Initialized to be 0x2D when CPU is powered up.
Fig 4-1 HWENW Action
HWENW: (accompanied with arguments HWWIDL and HWPS[2:0]):
12
[enabled]: In addition to power-up, the external reset will also force CPU to boot from ISP-memory, if ISP-
[disabled]: Where CPU boots from is determined by HWBS.
[enabled]: Code dumped on a universal Writer or Programmer is scrambled for security.
[disabled]: Not scrambled.
[enabled]: Code is locked for security.
[disabled]: Not locked.
[enabled]: If CPU runs in AP-memory, the register WDTCR will be firmware-write-protected except the bit
[disabled]: The register WDTCR can be freely written by firmware.
[enabled]: Automatically enable Watch-dog Timer by hardware when CPU is powered up.
[disabled]: No action on Watch-dog Timer when CPU powered up.
WDTCR Register (Watch-Dog-Timer Control Register)
WRF
7
memory is configured.
CLRW.
If CPU runs in ISP-memory, the register WDTCR will be firmware-write-protected except the bits
CLRW, PS2, PS1 and PS0.
--
6
HWENW
ENW
(1) set ENW bit
(2) load HWWIDL into WIDL bit
(3) load HWPS[2:0] into PS[2:0] bits.
5
load
CLRW
4
HWWIDL
WIDL
3
load
MG84FL54B Data Sheet
PS2
2
HWPS[2:0]
PS1
1
load
PS0
0
MEGAWIN