mg84fl54b Megawin Technology, mg84fl54b Datasheet - Page 81

• Manufacturer Part Number: mg84fl54b
• Description: Full-speed Usb Micro-controller
• Manufacturer: Megawin Technology

CKCON2 (Address=BFH, Clock Control Register 2)
OSCDR0: On-chip XTAL oscillating driving control bits.
EN_PLL: PLL enable bit. 1: Enable; 0: Disable
PLL_RDY: It is a read only flag to indicate the PLL status on ready or not.
CK_SEL: System clock divider input select bit. 1: CLKin=48MHz; 0: CLKin=OSCin.
In the default state, the reset value of CKCON is 0x00 (CK_SEL=0, and CKS2/1/0=000B), so the system clock
is the XTAL1-pin signal. The user can modify CKCON at any time to get a new system clock, which will be
active just after the modifying is completed.
In the applications which don’t care the frequency of system clock, the user can fill CKS2~CKS0 bits with a non-
zero value to slow the system clock before entering idle mode to get power saving.
22.2. On-chip XTAL Oscillating Driving Control
To reduce the operating power consumption resulted from the XTAL oscillating circuit, a smart driving control
mechanism is designed. The control bit OSCDR0 in CKCON2 is used for the driving control. When powered on,
the bit is 0 that select the maximum driving to easily start the XTAL oscillating. And, after MCU successfully runs
up, the user can program the bit to some values that can keep XTAL oscillating stable. Refer to the following
table for the values.
MEGAWIN
7
-
OSCDR0
0 select the maximum driving, and 1 selects the minimum driving.
0
1
6
-
OSCDR0
5
Down to 1MHz(TBD)
Up to 32MHz(TBD)
XTAL ranges
4
-
MG84FL54B Data sheet
EN_USB
3
EN_PLL
2
PLL_RDY
1
CK_SEL
0
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