mg84fl54b Megawin Technology, mg84fl54b Datasheet - Page 73

• Manufacturer Part Number: mg84fl54b
• Description: Full-speed Usb Micro-controller
• Manufacturer: Megawin Technology

Bit4: TXDBM-- Transmit Endpoint Double Buffer Mode.
Bit3: RXISO-- Receive Isochronous Type Enable.
Bit2: RXEPEN-- Receive Endpoint Enable.
Bit1: TXISO-- Transmit Isochronous Type Enable.
Bit0: TXEPEN-- Transmit Endpoint Enable.
RXSTAT (Endpoint Receive Status Register, Endpoint-Indexed, Address=E2H, SYS/USB_reset=0000-0xxx,
Read/Write)
Bit7: RXSEQ-- Receive Endpoint Sequence Bit (read, conditional write).
Bit6: RXSETUP-- Received Setup Transaction.
Bit5: STOVW-- Start Overwrite Flag (read-only).
Bit4: EDOVW-- End Overwrite Flag.
Bit3: RXSOVW-- Receive Data Sequence Overwrite Bit.
Bit2: ISOOVW-- Isochronous receive data Overwrite Bit.
Bit1~0: Reserved.
RXDAT (Receive FIFO Data Register, Endpoint-Indexed, Address=E3H, SYS/USB_reset=xxxx-xxxx, Read-only)
Bit7~0: RXD[7:0]-- Receive FIFO Data.
MEGAWIN
RXSEQ
RXD7
7
7
Set this bit to enable the double buffer transfer for IN transaction. Default is cleared.
This bit is only valid for endpoint 2.
Set this bit to configure the endpoint for Isochronous-Out transfer type. When disabled, the endpoint is for
Bulk/Interrupt-Out transfer type. The default value is 0.
This bit is only valid for endpoint 3 receive mode.
Set this bit to enable the receive endpoint. When disabled, the endpoint does not respond to a valid OUT
or SETUP token. This bit in endpoint 0 is enabled after reset.
Set this bit to configure the endpoint for Isochronous-In transfer type. When disabled, the endpoint is for
Bulk/Interrupt-In transfer type. The default value is 0.
This bit is only valid for endpoint 2.
Set this bit to enable the transmit endpoint. When disabled, the endpoint does not respond to a valid IN
token. This bit in endpoint 0 is enabled after reset.
The bit will be toggled on completion of an ACK handshake in response to an OUT token. This bit can be
written by firmware if the RXOVW bit is set when written along with the new RXSEQ value.
This bit is set by hardware when a valid SETUP transaction has been received. Clear this bit upon
detection of a SETUP transaction or the firmware is ready to handle the data/status stage of control
transfer.
Set by hardware upon receipt of a SETUP token for the control endpoint to indicate that the receive FIFO
is being overwritten with new SETUP data. This bit is used only for control endpoints.
This flag is set by hardware during the handshake phase of a SETUP transaction. This bit is cleared by
firmware to read the FIFO data. This bit is only used for control endpoints.
Write '1' to this bit to allow the value of the RXSEQ bit to be overwritten. Writing a '0' to this bit has no
effect on RXSEQ. This bit always returns '0' when read.
This bit is set by hardware as a FIFO access conflict happen when uc read the last data and usb host send
the next data in the same time. Firmware can use this bit to make sure whether the data had been
overwritten or not. When this bit is set, Firmware should write ‘0’ to clear this bit.
RXSETUP
RXD6
6
6
STOVW
RXD5
5
5
EDOVW
RXD4
4
4
MG84FL54B Data sheet
RXSOVW
RXD3
3
3
ISOOVW
RXD2
2
2
RXD1
1
1
-
RXD0
0
0
-
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