mg84fl54b Megawin Technology, mg84fl54b Datasheet - Page 65

• Manufacturer Part Number: mg84fl54b
• Description: Full-speed Usb Micro-controller
• Manufacturer: Megawin Technology

18.2. WDT During Idle and Power Down
In the Idle mode, the WIDL bit (WDTCR.3) determines whether WDT counts or not. Set this bit to let WDT keep
counting in the Idle mode.
18.3. WDT Automatically Enabled by Hardware
In addition to being initialized by software, the WDTCR register can also be automatically initialized at power-up
by the hardware options HWENW, HWWIDL and HWPS[2:0], which should be programmed by a universal
Writer or Programmer, as described below.
WDTCR register at power-up:
(1) set ENW bit,
(2) load HWWIDL into WIDL bit, and
(3) load HWPS[2:0] into PS[2:0] bits.
For example:
18.4. WDT Overflow Period
The WDT overflow period is determined by the formula:
The following Table shows the WDT overflow period for MCU running at 6MHz and 12MHz. The period is the
maximum interval for the user to clear the WDT to prevent from chip reset.
Table: WDT Overflow Period at Fosc = 6MHz & 12MHz
If HWENW is programmed to “enabled”, then hardware will automatically do the following initialization for the
MEGAWIN
PS2 PS1 PS0
If HWWIDL and HWPS[2:0] are programmed to be 1 and 5, respectively, then WDTCR will be initialized to be
0x2D when MCU is powered up, as shown below.
0
0
0
0
1
1
1
1
2
15
0
0
1
1
0
0
1
1
x (12 x Prescaler / Fosc), or 2
0
1
0
1
0
1
0
1
Prescaler value
128
256
16
32
64
2
4
8
15
x (12 x Prescaler / RCosc).
MG84FL54B Data sheet
65