mg84fl54b Megawin Technology, mg84fl54b Datasheet - Page 71

• Manufacturer Part Number: mg84fl54b
• Description: Full-speed Usb Micro-controller
• Manufacturer: Megawin Technology

Bit2: EFSR-- Enable USB Function’s Suspend/Resume interrupt.
Bit1: EF-- Enable USB Function’s interrupt Flag.
Bit0: Reserved.
UIE (USB Interrupt Enable Register, Address=DAH, SYS/USB_reset=00x0-x000, Read/Write)
Bit7: SOFIE-- Host SOF received Interrupt Enable.
If this bit is set, enables the Host SOF received interrupt. Default is cleared.
Bit6: ASOFIE-- ART SOF received Interrupt Enable.
If this bit is set, enables the ART SOF received interrupt. Default is cleared.
Bit5: Reserve.
Bit4: UTXIE2-- Function Transmit Interrupt Enable 2.
Bit3: Reserved.
Bit2: UTXIE1-- Function Transmit Interrupt Enable 1.
Bit1: URXIE0-- Function Receive Interrupt Enable 0.
Bit0: UTXIE0-- Function Transmit Interrupt Enable 0.
UIFLG (USB Interrupt Flag Register, Address=DBH, SYS/USB_reset=00x0-x000, Read/Write)
Bit7: SOFIF-- Host SOF received Interrupt Flag.
Bit6: ASOFIF-- ART SOF received Interrupt Flag.
Bit5: Reserved.
Bit4: UTXD2-- USB Transmit Done Flag for endpoint 2.
Bit3: Reserved.
Bit2: UTXD1-- USB Transmit Done Flag for endpoint 1.
MEGAWIN
SOFIE
SOFIF
7
7
If this bit is set, enables function’s interrupt of UPCON events. Function suspend/resume/remote-
wakeup/USB-reset interrupt enable bit. This bit doesn't be reset USB_RESET. Default is cleared.
If this bit is set, enables function’s interrupt of UIFLG. Transmit/receive done interrupt enable bit for USB
function endpoints. This bit doesn't be reset by USB_RESET. Default is cleared.
If this bit is set, enables the transmit done interrupt for USB endpoint 2 (UTXD2). Default is cleared.
If this bit is set, enables the transmit done interrupt for USB endpoint 1 (UTXD1). Default is cleared.
If this bit is set, enables the receive done interrupt for USB endpoint 0 (URXD0). Default is cleared.
If this bit is set, enables the transmit done interrupt for USB endpoint 0 (UTXD0). Default is cleared.
This bit is set by hardware when detected a host SOF. UC can read/write-clear on this bit. This bit is
cleared when firmware writes '1' to it.
This bit is set by hardware when detected an ART SOF. UC can read/write-clear on this bit. This bit is
cleared when firmware writes '1' to it.
This bit is set by hardware when detected a transmit done on endpoint 2. UC can read/write-clear on this
bit. This bit is cleared when firmware writes '1' to it.
This bit is set by hardware when detected a transmit done on endpoint 1. UC can read/write-clear on this
bit. This bit is cleared when firmware writes '1' to it.
ASOFIE
ASOFIF
6
6
5
5
-
-
UTXIE2
UTXD2
4
4
MG84FL54B Data sheet
3
3
-
-
UTXIE1
UTXD1
2
2
URXIE0
URXD0
1
1
UTXIE0
UTXD0
0
0
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