SST34WA3283 Silicon Storage Technology, Inc., SST34WA3283 Datasheet - Page 61

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SST34WA3283

Manufacturer Part Number
SST34WA3283
Description
32 Mbit Burst Mode Concurrent Superflash Combomemory 32 Mbit Burst Mode Concurrent Superflash Combomemory
Manufacturer
Silicon Storage Technology, Inc.
Datasheet
32 Mbit Burst Mode Concurrent SuperFlash ComboMemory
SST34WA32A3 / SST34WA32A4 / SST34WA3283 / SST34WA3284
©2007 Silicon Storage Technology, Inc.
FIGURE 33: PSRAM Continuous Burst Write with Output Delay BCR[8] = 1 for end-of-row Condition
A/DQ
LBS#/UBS#
Notes: 1. Default BCR settings for continuous burst WRITE, BCR[8] = 1: WAIT active LOW. WAIT asserted one data
A
15
max
–A/DQ
BES#
AVD#
WAIT
–A
WE#
OE#
CLK
2. BES# must not remain LOW longer than T
3. The Chip Enable signal, BES# must go High before the fourth Clock cycle after the WAIT signal goes Low.
16
cycle before delay.
If BCR[8] were set to 0, BES# would have to go Low before the third Clock cycle after WAIT signal goes Low.
0
VIH
VIH
VIH
VIL
VIL
T
T
CWS
CLK
T
Valid Input Valid Input
SPS
T
HDS
END OF ROW
(A6-A0: 7Fh)
T
BHZS
BEPS
61
Note 3
.
T
BHZS
High-Z
Advance Information
S71358-01-000
1358 F34.0
11/07

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