SST34WA3283 Silicon Storage Technology, Inc., SST34WA3283 Datasheet - Page 10

• Manufacturer Part Number: SST34WA3283
• Description: 32 Mbit Burst Mode Concurrent Superflash Combomemory 32 Mbit Burst Mode Concurrent Superflash Combomemory
• Manufacturer: Silicon Storage Technology, Inc.

Advance Information
Toggle Bits (DQ6 and DQ2)
During the internal Program or Erase operation, any
consecutive attempts to read DQ6 will produce alternating
‘1’s and ‘0’s. For example, toggling between ‘1’ and ‘0’.
When the internal Program or Erase operation is complete,
the DQ6 bit will stop toggling. The device is then ready for
the next operation. For Sector-, Block-, or Chip-Erase, the
toggle Bit (DQ6) is valid after the rising edge of sixth WE#
pulse. DQ6 will be set to ‘1’ if a Read operation is
attempted on an Erase-Suspended Sector/Block. If the
Program operation is initiated in a sector/block not selected
for Erase-Suspend mode, DQ6 will toggle. An additional
Toggle Bit is available on DQ2, which can be used in
conjunction with DQ6 to check whether a particular sector
is being actively erased or erase-suspended. Table 6
shows detailed status bit information. The Toggle Bit (DQ2)
is valid after the rising edge of the last WE# pulse of the
Write operation. See Figure 17 for Toggle Bit the timing
diagram and Figure 48 for a flowchart.
TABLE 6: Write Operation Status
Note: Note: DQ7, DQ6 and DQ2 require a valid address when
©2007 Silicon Storage Technology, Inc.
Status
Normal
Operation
Erase-
Suspend
Mode
reading status information. When in Erase-Suspend Mode
the system can read either synchronously (Burst) or asyn-
chronously.
Standard
Program
Standard
Erase
Read from
Erase-Sus-
pended Sec-
tor/Block
Read from
Non- Erase-
Suspended
Sector/Block
Program
SST34WA32A3 / SST34WA32A4 / SST34WA3283 / SST34WA3284
DQ7# Toggle
DQ7# Toggle
Data
DQ7
0
1
32 Mbit Burst Mode Concurrent SuperFlash ComboMemory
Toggle
DQ6
Data
1
DQ5
Data
0
0
0
0
Toggle
Toggle
Toggle
T6.0 1358
DQ2
Data
N/A
No
10
Data Protection
The
hardware and software features to protect flash memory
data from inadvertent writes.
Hardware Data Protection
The device provides the following protection features to
prevent inadvertent writes to the flash memory:
A
When the A
Eight Word Program command is enabled. In this case all
blocks are temporarily unprotected regardless of the Block
Locking Register. The only device operation available when
A
must not be held above
Word Programming is provided for fast data programming
in the manufacturing environment. The device will return to
normal operations when voltage is set to
and each block locking status will depend on the Block
Locking Register value (this is the value that each block
had before the application of V
not be left floating or unconnected.
When the A
The A
chip operations.
WP# Pin
The SST34WA32A3/32A4/3283/3284 provides a hard-
ware block protection which protects the 8 KWords for
Blocks BA0 and BA1 (SST34WA32x3), and/or BA65 and
BA66 (SST34WA32x4) of the flash memory. BAx stands
for Block Address.
The 8 KWord blocks, located in the top or bottom blocks,
are protected when WP# is held to V
Erase operation in these blocks is disabled independently
using the Block Locking Register Status. The user can
disable the hardware protection for the outermost blocks by
driving WP# to
two outermost Blocks will revert to what is indicated by the
corresponding Block Locking Registers. WP# will be
latched at a specific time in the program or erase
sequence. To prevent a write to the outermost blocks, WP#
must be held to
For example, the 4th write cycle in the program sequence
and the 6th write cycle in the erase sequence. If using the
CC
CC
– Noise/Glitch Protection: A WE# or BEF# pulse of
–
– Write Inhibit Mode: Forcing OE# low, BEF# high, or
pin is at V
Pin
less than 5 ns will not initiate a write cycle.
V
is inhibited when
WE# high will inhibit the Write operation. This pre-
vents inadvertent writes during power-up or power-
down.
CC
SST34WA32A3/32A4/3283/3284
DD
pin should be at
Power Up/Down Detection: The Write operation
CC
CC
H
V
pin is brought to
pin is brought to the Supervoltage VH the
V
IH
is Eight Word Programming, the A
IL
. In this case, the Protection Status of the
on the last write cycle of the sequence.
V
DD
V
IH
V
is less than V
during other operations. Eight
IH
H
for all other conditions and
on A
V
IL
CC
all sectors are locked.
IL
). The A
. The Program and
S71358-01-000
LKO
provides
V
.
IH
CC
on A
pin must
CC
CC
both
11/07
pin
pin