SST34WA3283 Silicon Storage Technology, Inc., SST34WA3283 Datasheet - Page 19

• Manufacturer Part Number: SST34WA3283
• Description: 32 Mbit Burst Mode Concurrent Superflash Combomemory 32 Mbit Burst Mode Concurrent Superflash Combomemory
• Manufacturer: Silicon Storage Technology, Inc.

32 Mbit Burst Mode Concurrent SuperFlash ComboMemory
SST34WA32A3 / SST34WA32A4 / SST34WA3283 / SST34WA3284
PSRAM
Self-Initialization
On the power-up of the PSRAM, a self-initialization process
begins. During the initialization V
simultaneously applied and BES# must remain High. Self-
initialization requires 150µs after V
at or above 1.7V. After completion of the self-initialization,
the default settings for the Bus Configuration Register
(BCR) and the Refresh Configuration Register (RCR) are
configured and the device is ready for normal operation.
Asynchronous Mode
The device configuration on power-up is Asynchronous
Random Read. To read data from the PSRAM memory
array, the system must assert a valid address on the
multiplexed address/data bus while BES# and AVD# are at
V
AVD# latches the address, and OE# is driven to V
data appears on A/DQ
To write data, drive BES#, WE#, and LBS#/UBS# to V
while a valid address is asserted on the multiplexed
address/data bus. Driving AVD# to V
and drives the data onto the bus. OE# is in a “don’t care”
state during Asynchronous Random Write mode, and WE#
can override OE#. To terminate the Write operation, de-
assert BES#, WE#, and LBS#/UBS#. See Table 18 for
details of the PSRAM bus operation during Asynchronous
mode.
Burst Mode
High-speed, synchronous PSRAM Read and Write are
enabled by burst mode operation. The access address
latches on the next clock after AVD# and BES# are driven
low. Read or Write is indicated by WE# during the first clock
rising edge. Fixed-length bursts of 4-, 8-, or 16-words or
continuous, bursts are selected in the BCR.
Latency is the number of clock cycles before the initial data
is transferred between the processor and the PSRAM, and
is set in the BCR. Initial Read latency is configured as
either fixed or variable; however, Write latency is always
fixed. To achieve minimum latency at high clock
frequencies, configure the Burst PSRAM to variable
©2007 Silicon Storage Technology, Inc.
V
IL
DD
FIGURE 3: Power-Up Initialization Timing
. During the read, WE# remains at
, V
DDQ
V
DD
= 1.7V
15
- A/DQ
Device Initialization
T
PUS > 150µs
0
after T
DD
DD
IH
V
and V
and V
IH
latches the address
BES
, the rising edge of
Device ready for
normal operation
.
DDQ
DDQ
are stable
1358 F55.0
must be
IL
. The
IL
19
latency. This requires the controller to monitor WAIT for
refresh cycle conflicts.
Fixed latency improves performance at lower clock
frequencies by sending the first data word after the worst
case access delay. Use this feature when the controller
cannot monitor the WAIT.
When a burst initiates, WAIT is asserted; and is then de-
asserted when data is to be transferred into, or out of, the
memory.
Stopping the CLK at High or Low suspends Bursts. While
burst is suspended, if another device uses the data bus
then OE# must be driven High to disable the outputs.
Otherwise, OE# can remain Low. During the burst
suspend, WAIT remains active and no other devices can
share the WAIT connection to the controller. To resume the
burst, drive OE# Low. After valid data is available on the
bus, CLK is restarted.
The refresh cycle limits the time that BES# can stay low. If
BES# remains Low due to a burst suspend longer than
T
restarted with BES# Low / AVD# Low cycle. See Table 19
for details of the PSRAM bus operation at Burst mode.
Mixed Mode
Mixed
Asynchronous Write to seamlessly interface with legacy
burst mode flash memory controllers; and is supported
when the BCR is configured for synchronous operation.
Hold the CLK low for the entire sequence for asynchronous
Write. Latch the target address using AVD#. When
transitioning between mixed more and fixed latency
enabled, BES# can be driven High. BES# Low must not
exceed T
WAIT
WAIT
SST34WA32A3/32A4/3283/3284 internally. This signal
coordinates transactions on the synchronous bus in
multiple memory systems.
After Read or Write is initiated, WAIT activates because in
burst mode, PSRAM requires additional time before
transferring data. For Reads, WAIT is active until valid data
is output; for Writes, WAIT indicated when data can be
accepted. Data burst progresses on successive rising clock
edges when WAIT is inactive. Until the first data is valid,
BES# must remain asserted. To prevent data corruption,
do not bring BES# High during the initial latency.
If Read launches during an on-chip refresh and when using
variable initial access latency (BCR[14] = 0), WAIT
BEPS
, then BES# must be driven High and the burst
output
mode
BEPS
.
connects
combines
to
synchronous
the
Advance Information
RY/BY#
S71358-01-000
Read
of
and
11/07
the