SST34WA3283 Silicon Storage Technology, Inc., SST34WA3283 Datasheet - Page 3

• Manufacturer Part Number: SST34WA3283
• Description: 32 Mbit Burst Mode Concurrent Superflash Combomemory 32 Mbit Burst Mode Concurrent Superflash Combomemory
• Manufacturer: Silicon Storage Technology, Inc.

32 Mbit Burst Mode Concurrent SuperFlash ComboMemory
SST34WA32A3 / SST34WA32A4 / SST34WA3283 / SST34WA3284
Asynchronous Read
The default configuration of the flash memory on power-up,
or after a hardware reset via the RST# pin, is
Asynchronous Read. To read data from the flash memory
array, the system must assert a valid address on A/DQ
A/DQ
During the read, WE# remains at V
Asynchronous Read, the rising edge of AVD# latches the
address, and OE# is driven to V
DQ
array is divided into four banks, each bank remains enabled
for read access until the command register contents are
altered.
Address access time (T
stable addresses to valid output data. The chip enable
access time (T
and stable BEF# to valid data at the outputs. The output
enable access time (T
of OE# to valid data at the output.
The internal state machine is set to read array data upon
device power-up or after a hardware reset. This ensures
that no spurious alteration of the memory content occurs
during the power transition.
Burst Mode Read (Synchronous)
The
default configuration on power-up or after reset is
Asynchronous Read. However, it can be configured to
operate in a Synchronous Read mode with a continuous,
©2007 Silicon Storage Technology, Inc.
FIGURE 1: Synchronous/Asynchronous State Diagram
15
–A/DQ
0
SST34WA32A3/32A4/3283/3284
and A
0.
20
For details, see Figure 9. Since the memory
CE
–A
) is the delay from the stable addresses
16
, while AVD# and BEF# are at
OE
) is the delay from the falling edge
ACC
) is equal to the delay from
IL
. The data appears on A/
when AVD# is low
IH
Active CLK edge
and CLK is X for
flash
memory
Asynchronous Read
Synchronous Read
Hardware Reset
V
Mode Only
Mode Only
15
Power-up/
IL
–
.
3
sequential linear burst operation or a linear burst operation
of 8-, 16-, or 32-words length with wrap-around.
Before setting the flash memory configuration to Burst
Mode, determine the number of wait states for the initial
word access time (T
continuous with, or without, wrap-around.
WAIT States
On power up, the flash memory of SST34WA32A3/32A4/
3283/3284 defaults to asynchronous read operation. The
device is automatically enabled for burst mode on the first
rising edge on the CLK input, while the AVD# is held low
and the addresses are latched on the first rising edge of the
CLK. Prior to activating the clock signal, the system
determines how many wait states are desired for the initial
word (T
the Set Configuration Register command sequence.
The device automatically delays RY/BY# by the needed
number of clock cycles if data is not ready. Refer to the
details in “Handshaking Feature” section.
The initial word is output on the Data Bus T
active edge of the first CLK cycle. Each successive clock
cycle automatically increments the addresses counter.
Subsequent words are output on the Data Bus T
the active edge of each successive clock cycle.
To return the device to Asynchronous Read mode, either
drive BEF# to
BEF# VIH
RST# VIL
IACC
) of each burst session. The system then writes
V
1358 F01.0
IH
or drive RST# to
IACC
) and the desired Burst mode—
V
Advance Information
IL
.
S71358-01-000
IACC
BACC
after the
after
11/07