SST34WA3283 Silicon Storage Technology, Inc., SST34WA3283 Datasheet - Page 49

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SST34WA3283

Manufacturer Part Number
SST34WA3283
Description
32 Mbit Burst Mode Concurrent Superflash Combomemory 32 Mbit Burst Mode Concurrent Superflash Combomemory
Manufacturer
Silicon Storage Technology, Inc.
Datasheet
32 Mbit Burst Mode Concurrent SuperFlash ComboMemory
SST34WA32A3 / SST34WA32A4 / SST34WA3283 / SST34WA3284
©2007 Silicon Storage Technology, Inc.
FIGURE 19: Flash Boundary Crossing into Program/Erase Bank
FIGURE 20: Example of Flash WAIT State Insertion
Note: Cxxx indicates which clock triggers Dxxx at the output. For example, C253 triggers D253.
A/DQ
Note: Figure assumes address. D0 is not an address boundary, active clock edge is rising, and wait state is set to ‘101.’
Address (hex)
A/DQ
BEF#/OE#
15
The figure shows that the device cross a bank when performing an erase or program operation.
RY/BY#
-A/DQ
15
AVD#
-A/DQ
CLK
AVD#
OE#
CLK
Wait State Decoding Addresses:
A14, A13, A12 = “101” => 5 programmed, 7 total
A14, A13, A12 = “100” => 4 programmed, 6 total
A14, A13, A12 = “011” => 3 programmed, 5 total
A14, A13, A12 = “010” => 2 programmed, 4 total
A14, A13, A12 = “001” => 1 programmed, 3 total
0
0
(stays low)
(stays high)
(stays high)
C253
3FFFD
D253
C254
3FFFE
1
D254
Total number of clock cycles following AVD# falling edge
C255
3FFFF
0
2
D255
C256
Number of clock cycles programmed
40000
3
1
49
C257
40001
4
2
Read Status
following last wait state triggers
5
Rising edge of next clock cycle
3
next burst data
6
4
7
5
D0
1358 F19.0
Advance Information
D1
S71358-01-000
1358 F18.0
11/07

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