SST34WA3283 Silicon Storage Technology, Inc., SST34WA3283 Datasheet - Page 57

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SST34WA3283

Manufacturer Part Number
SST34WA3283
Description
32 Mbit Burst Mode Concurrent Superflash Combomemory 32 Mbit Burst Mode Concurrent Superflash Combomemory
Manufacturer
Silicon Storage Technology, Inc.
Datasheet
32 Mbit Burst Mode Concurrent SuperFlash ComboMemory
SST34WA32A3 / SST34WA32A4 / SST34WA3283 / SST34WA3284
©2007 Silicon Storage Technology, Inc.
FIGURE 28: PSRAM Continuous Burst Read with Output Delay BCR[8] = 1 for variable latency end-of-
A/DQ
Note: 1. Default BCR settings for continuous burst READ, BCR[8] = 1: WAIT active LOW; WAIT asserted one data cycle
LBS#/UBS#
A
15
max
–A/DQ
2. BES# must not remain LOW longer than T
3. The Chip Enable signal, BCR8 were set to 1, BES# would have to go Low before the fourth Clock cycle after
row condition
ADV#
BES#
WAIT
–A
WE#
CLK
OE#
before delay. Do not cross row boundaries.
WAIT signal goes Low.
16
0
VIH
VIL
VIL
VIL
T
T
CLK
CWS
Valid Output
Valid Output
(A8-A0: 7Fh)
End of Row
BEPS
T
.
Note 3
BHZS
57
T
BHZS
Advance Information
S71358-01-000
1358 F29.0
HIgh-Z
11/07

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