upd78f0148m1gka1-9eu Renesas Electronics Corporation., upd78f0148m1gka1-9eu Datasheet - Page 656

• Manufacturer Part Number: upd78f0148m1gka1-9eu
• Description: 8-bit Single-chip Microcontrollers
• Manufacturer: Renesas Electronics Corporation.

656
Serial
interface
CSIA0
Multiplier/
divider
Interrupt
Function
Repeat
transmission
mode
Automatic
transmission/
reception
suspension and
restart
Busy control
Busy & strobe
control
SDR0:
Remainder data
register 0
MDA0H, MDA0L:
Multiplication/
division data
register A0
MDB0:
Multiplication/
division data
register B0
DMUC0:
Multiplier/divider
control register 0
IF1H: Interrupt
request flag
register
IF0L, IF0H, IF1L,
IF1H: Interrupt
request flag
registers
Details of
Function
Because, in the repeat transmission mode, a read is performed on the buffer
RAM after the transmission of one byte, the interval is included in the period up to
the next transmission. As the buffer RAM read is performed at the same time as
CPU processing, the interval is dependent upon automatic data transfer interval
specification register 0 (ADTI0) and the set values of bits 5 and 4 (STBE0,
BUSYE0) of serial status register 0 (CSIS0) (see (5) Automatic transmit/receive
interval time).
If the HALT instruction is executed during automatic transmission/reception,
communication is suspended and the HALT mode is set if during 8-bit data
communication. When the HALT mode is cleared, automatic
transmission/reception is restarted from the suspended point.
When suspending automatic transmission/reception, do not change the operating
mode to 3-wire serial I/O mode while TSF0 = 1.
Busy control cannot be used simultaneously with the interval time control function
of automatic data transfer interval specification register 0 (ADTI0).
When TSF0 is cleared, the SOA0 pin goes low.
The value read from SDR0 during operation processing (while bit 7 (DMUE) of
multiplier/divider control register 0 (DMUC0) is 1) is not guaranteed.
SDR0 is reset when the operation is started (when DMUE is set to 1).
MDA0H is cleared to 0 when an operation is started in the multiplication mode
(when multiplier/divider control register 0 (DMUC0) is set to 81H).
Do not change the value of MDA0 during operation processing (while bit 7
(DMUE) of multiplier/divider control register 0 (DMUC0) is 1). Even in this case,
the operation is executed, but the result is undefined.
The value read from MDA0 during operation processing (while DMUE is 1) is not
guaranteed.
Do not change the value of MDB0 during operation processing (while bit 7
(DMUE) of multiplier/divider control register 0 (DMUC0) is 1). Even in this case,
the operation is executed, but the result is undefined.
Do not clear MDB0 to 0000H in the division mode. If set, undefined operation
results are stored in MDA0 and SDR0.
If DMUE is cleared to 0 during operation processing (when DMUE is 1), the
operation result is not guaranteed. If the operation is completed while the
clearing instruction is being executed, the operation result is guaranteed,
provided that the interrupt flag is set.
Do not change the value of DMUSEL0 during operation processing (while DMUE
is 1). If it is changed, undefined operation results are stored in
multiplication/division data register A0 (MDA0) and remainder data register 0
(SDR0).
If DMUE is cleared to 0 during operation processing (while DMUE is 1), the
operation processing is stopped. To execute the operation again, set
multiplication/division data register A0 (MDA0), multiplication/division data
register B0 (MDB0), and multiplier/divider control register 0 (DMUC0), and start
the operation (by setting DMUE to 1).
Be sure to clear bits 5 to 7 of IF1H to 0.
When operating a timer, serial interface, or A/D converter after standby release,
operate it once after clearing the interrupt request flag. An interrupt request flag
may be set by noise.
APPENDIX D LIST OF CAUTIONS
User’s Manual U15947EJ3V1UD
Cautions
p. 398
p. 403
p. 403
p. 404
p. 406
p. 411
p. 411
p. 412
p. 412
p. 412
p. 413
p. 413
p. 414
p. 414
p. 414
p. 425
p. 425
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