upd78f0148m1gka1-9eu Renesas Electronics Corporation., upd78f0148m1gka1-9eu Datasheet - Page 199

• Manufacturer Part Number: upd78f0148m1gka1-9eu
• Description: 8-bit Single-chip Microcontrollers
• Manufacturer: Renesas Electronics Corporation.

(6) Operation of OVF0n flag
(7) Conflicting operations
<1> The OVF0n flag is also set to 1 in the following case.
<2> Even if the OVF0n flag is cleared before the next count clock is counted (before TM0n becomes 0001H)
If a conflict occurs between the read period of the 16-bit timer capture/compare register (CR00n/CR01n) and
capture trigger input (CR00n/CR01n used as capture register), the priority is given to the capture trigger input.
The data read from CR00n/CR01n is undefined.
Remark n = 0:
When any of the following modes is selected: the mode in which clear & start occurs on a match between
TM0n and CR00n, the mode in which clear & start occurs at the TI00n valid edge, or the free-running mode
TM0n is counted up from FFFFH to 0000H.
after the occurrence of TM0n overflow, the OVF0n flag is re-set newly so this clear is invalid.
CR01n capture value
n = 0, 1:
Capture read signal
TM0n count value
CR00n is set to FFFFH
Count clock
Edge input
INTTM01n
µ
µ
PD780143, 780144
PD780146, 780148, 78F0148
Count clock
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01
INTTM00n
↓
↓
Figure 7-42. Capture Register Data Retention Timing
OVF0n
CR00n
TM0n
Figure 7-41. Operation Timing of OVF0n Flag
X
N
FFFEH
FFFFH
User’s Manual U15947EJ3V1UD
N + 1
FFFFH
Capture
N + 2
0000H
0001H
N + 2
M
Capture, but
read value is
not guaranteed
M + 1
M + 1
M + 2
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