upd78f0148m1gka1-9eu Renesas Electronics Corporation., upd78f0148m1gka1-9eu Datasheet - Page 425

• Manufacturer Part Number: upd78f0148m1gka1-9eu
• Description: 8-bit Single-chip Microcontrollers
• Manufacturer: Renesas Electronics Corporation.

(1) Interrupt request flag registers (IF0L, IF0H, IF1L, IF1H)
Note
Cautions 1. Be sure to clear bits 5 to 7 of IF1H to 0.
The interrupt request flags are set to 1 when the corresponding interrupt request is generated or an instruction is
executed. They are cleared to 0 when an instruction is executed upon acknowledgment of an interrupt request or
upon RESET input.
When an interrupt is acknowledged, the interrupt request flag is automatically cleared and then the interrupt
routine is entered.
IF0L, IF0H, IF1L, and IF1H are set by a 1-bit or 8-bit memory manipulation instruction. When IF0L and IF0H, and
IF1L and IF1H are combined to form 16-bit registers IF0 and IF1, they are set by a 16-bit memory manipulation
instruction.
RESET input clears these registers to 00H.
Address: FFE0H After reset: 00H R/W
Symbol
IF0L
Address: FFE1H
Symbol
IF0H
Address: FFE2H
Symbol
IF1L
Address: FFE3H
Symbol
IF1H
µ
PD780146, 780148, and 78F0148 only. Be sure to clear these bits to 0 in the
2. When operating a timer, serial interface, or A/D converter after standby release, operate it
Figure 19-2. Format of Interrupt Request Flag Registers (IF0L, IF0H, IF1L, IF1H)
once after clearing the interrupt request flag. An interrupt request flag may be set by noise.
TMIF010
SREIF6
XXIFX
PIF7
<7>
<7>
<7>
7
0
0
1
After reset: 00H
After reset: 00H
After reset: 00H
No interrupt request signal is generated
Interrupt request signal is generated, interrupt request status
TMIF000
PIF5
PIF6
<6>
<6>
<6>
6
0
CHAPTER 19 INTERRUPT FUNCTIONS
R/W
R/W
R/W
TMIF50
WTIF
PIF4
<5>
<5>
<5>
User’s Manual U15947EJ3V1UD
5
0
TMIFH0
ACSIIF
KRIF
PIF3
<4>
<4>
<4>
<4>
Interrupt request flag
TMIF011
TMIFH1
TMIF51
PIF2
<3>
<3>
<3>
<3>
Note
TMIF001
DUALIF0
WTIIF
PIF1
<2>
<2>
<2>
<2>
Note
µ
CSIIF11
PD780143 and 780144.
STIF6
SRIF0
PIF0
<1>
<1>
<1>
<1>
Note
DMUIF
SRIF6
LVIIF
ADIF
<0>
<0>
<0>
<0>
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