upd78f0148m1gka1-9eu Renesas Electronics Corporation., upd78f0148m1gka1-9eu Datasheet - Page 645

• Manufacturer Part Number: upd78f0148m1gka1-9eu
• Description: 8-bit Single-chip Microcontrollers
• Manufacturer: Renesas Electronics Corporation.

16-bit
timer/
event
counters
00, 01
(TM00,
TM01)
Function
16-bit timer
capture/
compare
register 00n
setting
Capture register
data retention
timing
Valid edge
setting
One-shot pulse
output:
Software trigger
One-shot pulse
output: External
trigger
One-shot pulse
output function
Operation of
OVF0n flag
Conflicting
operations
Timer operation
Capture
operation
Compare
operation
Details of
Function
In the mode in which clear & start occurs on a match between TM0n and CR00n,
set 16-bit timer capture/compare register 00n (CR00n) to other than 0000H. This
means a 1-pulse count operation cannot be performed when 16-bit timer/event
counter 0n is used as an external event counter.
The values of 16-bit timer capture/compare registers 00n and 01n (CR00n and
CR01n) are not guaranteed after 16-bit timer/event counter 0n has been stopped.
Set the valid edge of the TI00n pin after clearing bits 2 and 3 (TMC0n2 and
TMC0n3) of 16-bit timer mode control register 0n (TMC0n) to 0, 0, respectively,
and then stopping timer operation. The valid edge is set using bits 4 and 5
(ES0n0 and ES0n1) of prescaler mode register 0n (PRM0n).
Do not set the OSPT0n bit to 1 again while the one-shot pulse is being output. To
output the one-shot pulse again, wait until the current one-shot pulse output is
completed.
Do not input the external trigger again while the one-shot pulse is being output.
To output the one-shot pulse again, wait until the current one-shot pulse output is
completed.
When using the one-shot pulse output of 16-bit timer/event counter 0n with a
software trigger, do not change the level of the TI00n pin or its alternate-function
port pin.
Because the external trigger is valid even in this case, the timer is cleared and
started even at the level of the TI00n pin or its alternate-function port pin, resulting
in the output of a pulse at an undesired timing.
The OVF0n flag is also set to 1 in the following case.
When any of the following modes is selected: the mode in which clear & start
occurs on a match between TM0n and CR00n, the mode in which clear & start
occurs at the TI00n valid edge, or the free-running mode
→ CR00n is set to FFFFH
→ TM0n is counted up from FFFFH to 0000H.
Even if the OVF0n flag is cleared before the next count clock is counted (before
TM0n becomes 0001H) after the occurrence of TM0n overflow, the OVF0n flag is
re-set newly so this clear is invalid.
If a conflict occurs between the read period of the 16-bit timer capture/compare
register (CR00n/CR01n) and capture trigger input (CR00n/CR01n used as capture
register), the priority is given to the capture trigger input. The data read from
CR00n/CR01n is undefined.
Even if 16-bit timer counter 0n (TM0n) is read, the value is not captured by 16-bit
timer capture/compare register 01n (CR01n).
Regardless of the CPU’s operation mode, when the timer stops, the input signals
to the TI00n/TI01n pins are not acknowledged.
The one-shot pulse output mode operates correctly only in the free-running mode
and the mode in which clear & start occurs at the TI00n valid edge. In the mode in
which clear & start occurs on a match between the TM0n register and CR00n
register, one-shot pulse output is not possible because an overflow does not
occur.
If TI00n valid edge is specified as the count clock, a capture operation by the
capture register specified as the trigger for TI00n is not possible.
To ensure the reliability of the capture operation, the capture trigger requires a
pulse longer than two cycles of the count clock selected by prescaler mode
register 0n (PRM0n).
The capture operation is performed at the falling edge of the count clock. An
interrupt request input (INTTM00n/INTTM01n), however, is generated at the rise
of the next count clock.
A capture operation may not be performed for CR00n/CR01n set in compare
mode even if a capture trigger has been input.
APPENDIX D LIST OF CAUTIONS
User’s Manual U15947EJ3V1UD
Cautions
p. 198
p. 198
p. 198
p. 198
p. 198
p. 198
p. 199
p. 199
p. 199
p. 200
p. 200
p. 200
p. 200
p. 200
p. 200
p. 200
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