upd78f0148m1gka1-9eu Renesas Electronics Corporation., upd78f0148m1gka1-9eu Datasheet - Page 377

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upd78f0148m1gka1-9eu

Manufacturer Part Number
upd78f0148m1gka1-9eu
Description
8-bit Single-chip Microcontrollers
Manufacturer
Renesas Electronics Corporation.
Datasheet
Address: FF94H
Address: FF93H
BRGCA0
Symbol
(4) Divisor selection register 0 (BRGCA0)
Symbol
(5) Automatic data transfer address point specification register 0 (ADTP0)
ADTP0
Caution Be sure to clear bits 7 to 5 to 0.
Figure 17-7. Format of Automatic Data Transfer Address Point Specification Register 0 (ADTP0)
This is an 8-bit register used to select the base clock divisor of CSIA0.
This register can be set by an 8-bit memory manipulation instruction. However, when bit 0 (TSF0) of serial
status register 0 (CSIS0) is 1, rewriting BRGCA0 is prohibited.
Remarks 1. Figures in parentheses apply to operation with f
This is an 8-bit register used to specify the buffer RAM address that ends transfer during automatic data
transfer (bit 6 (ATE0) of serial operation mode specification register 0 (CSIMA0) = 1).
This register can be set by an 8-bit memory manipulation instruction. However, when bit 0 (TSF0) of serial
status register 0 (CSIS0) is 1, rewriting ADTP0 is prohibited.
In the 78K0/KF1, 00H to 1FH can be specified because 32 bytes of buffer RAM are incorporated.
Example When ADTP0 is set to 07H
In repeat transfer mode (bit 5 (ATM0) of CSIMA0 = 1), transfer is performed repeatedly up to the address
specified with ADTP0.
Example When ADTP0 is set to 07H (repeat transfer mode)
BRGCA01
After reset: 00H
After reset: 03H
2. f
8 bytes of FA00H to FA07H are transferred.
Transfer is repeated as FA00H to FA07H, FA00H to FA07H, … .
7
0
7
0
0
0
1
1
W
: Base clock frequency selected by CKS00 bit of CSIS0 register
Figure 17-6. Format of Divisor Selection Register 0 (BRGCA0)
BRGCA00
6
0
6
0
0
1
0
1
R/W
R/W
CHAPTER 17 SERIAL INTERFACE CSIA0
f
f
f
f
W
W
W
W
/6 (1.67 MHz)
/2
/2
/2
3
4
5
(1.25 MHz)
(625 kHz)
(312.5 kHz)
5
0
5
0
User’s Manual U15947EJ3V1UD
ADTP04
4
4
0
CSIA0 base clock (f
ADTP03
W
3
3
0
= 10 MHz.
W
) divisor selection
ADTP02
2
2
0
BRGCA01
ADTP01
1
1
BRGCA00
ADTP00
0
0
377

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