upd78f0148m1gka1-9eu Renesas Electronics Corporation., upd78f0148m1gka1-9eu Datasheet - Page 255

• Manufacturer Part Number: upd78f0148m1gka1-9eu
• Description: 8-bit Single-chip Microcontrollers
• Manufacturer: Renesas Electronics Corporation.

11.3 Registers Controlling Watchdog Timer
(1) Watchdog timer mode register (WDTM)
Address: FF98H
The watchdog timer is controlled by the following two registers.
• Watchdog timer mode register (WDTM)
• Watchdog timer enable register (WDTE)
Symbol
WDTM
This register sets the overflow time and operation clock of the watchdog timer.
This register can be set by an 8-bit memory manipulation instruction and can be read many times, but can be
written only once after reset is released.
RESET input sets this register to 67H.
Notes 1.
WDCS4
WDCS2
7
0
0
0
1
0
0
0
0
1
1
1
1
2.
Note 1
Note 2
After reset: 67H
WDCS3
WDCS1
If “Internal oscillator cannot be stopped” is specified by a mask option, this cannot be set. The
internal oscillation clock will be selected no matter what value is written.
Reset is released at the maximum cycle (WDCS2, 1, 0 = 1, 1, 1).
Figure 11-2. Format of Watchdog Timer Mode Register (WDTM)
6
1
0
1
×
0
0
1
1
0
0
1
1
Note 1
Note 2
WDCS0
Internal oscillation clock (f
X1 input clock (f
Watchdog timer operation stopped
R/W
0
1
0
1
0
1
0
1
5
1
CHAPTER 11 WATCHDOG TIMER
Note 2
User’s Manual U15947EJ3V1UD
During internal oscillation clock
2
2
2
2
2
2
2
2
11
12
13
14
15
16
17
18
WDCS4
/f
/f
/f
/f
/f
/f
/f
/f
XP
R
R
R
R
R
R
R
R
4
)
(4.27 ms)
(8.53 ms)
(17.07 ms)
(34.13 ms)
(68.27 ms)
(136.53 ms)
(273.07 ms)
(546.13 ms)
operation
Operation clock selection
R
)
WDCS3
3
Overflow time setting
WDCS2
2
During X1 input clock operation
2
2
2
2
2
2
2
2
13
14
15
16
17
18
19
20
/f
/f
/f
/f
/f
/f
/f
/f
XP
XP
XP
XP
XP
XP
XP
XP
(819.2
(1.64 ms)
(3.28 ms)
(6.55 ms)
(13.11 ms)
(26.21 ms)
(52.43 ms)
(104.86 ms)
WDCS1
1
µ
s)
WDCS0
0
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