upd78f0148m1gka1-9eu Renesas Electronics Corporation., upd78f0148m1gka1-9eu Datasheet - Page 398

• Manufacturer Part Number: upd78f0148m1gka1-9eu
• Description: 8-bit Single-chip Microcontrollers
• Manufacturer: Renesas Electronics Corporation.

398
SCKA0
SOA0
(c) Repeat transmission mode
In this mode, data stored in the internal buffer RAM is transmitted repeatedly.
Serial communication is started when bit 0 (ATSTA0) of serial trigger register 0 (CSIT0) is set to 1 while
bit 7 (CSIAE0), bit 6 (ATE0), bit 5 (ATM0), and bit 3 (TXEA0) of serial operation mode specification
register 0 (CSIMA0) are set to 1.
Unlike the basic transmission mode, after the number of setting bytes has been transmitted, the interrupt
request flag (ACSIIF) is not set, automatic data transfer address count register 0 (ADTC0) is reset to 0,
and the internal buffer RAM contents are transmitted again.
When a reception operation, busy control and strobe control are not performed, the SIA0/P143,
BUSY0/BUZ/INTP7/P141, and STB0/P145 pins can be used as ordinary I/O port pins.
The repeat transmission mode operation timing is shown in Figure 17-19, and the operation flowchart in
Figure 17-20. Figure 17-21 shows the operation of the internal buffer RAM when 6 bytes of data are
transmitted in the repeat transmission mode.
Cautions 1. Because, in the repeat transmission mode, a read is performed on the buffer RAM
D7 D6 D5 D4 D3 D2 D1 D0
2. If an access to the buffer RAM by the CPU conflicts with an access to the buffer
Figure 17-19. Repeat Transmission Mode Operation Timing
after the transmission of one byte, the interval is included in the period up to the
next transmission. As the buffer RAM read is performed at the same time as CPU
processing, the interval is dependent upon automatic data transfer interval
specification register 0 (ADTI0) and the set values of bits 5 and 4 (STBE0, BUSYE0)
of serial status register 0 (CSIS0) (see (5) Automatic transmit/receive interval time).
RAM by serial interface CSIA0 during the interval period, the interval time specified
by automatic data transfer interval specification register 0 (ADTI0) may be extended.
CHAPTER 17 SERIAL INTERFACE CSIA0
User’s Manual U15947EJ3V1UD
Interval
D7 D6 D5 D4 D3 D2 D1 D0
Interval
D7 D6 D5