upd78f0148m1gka1-9eu Renesas Electronics Corporation., upd78f0148m1gka1-9eu Datasheet - Page 647

• Manufacturer Part Number: upd78f0148m1gka1-9eu
• Description: 8-bit Single-chip Microcontrollers
• Manufacturer: Renesas Electronics Corporation.

8-bit
timers H0,
H1
(TMH0,
TMH1)
Watch
timer
Function
TMHMD0: 8-bit
timer H mode
register 0
TMHMD1: 8-bit
timer H mode
register 1
PWM output
Carrier
generator mode
(TMH1 only)
WTM: Watch
timer operation
mode register
Interrupt
request
Details of
Function
When the internal oscillation clock is selected as the clock to be supplied to the
CPU, the clock of the internal oscillator is divided and supplied as the count clock.
If the count clock is the internal oscillation clock, the operation of 8-bit timer H0 is
not guaranteed.
When TMHE0 = 1, setting the other bits of the TMHMD0 register is prohibited.
In the PWM output mode, be sure to set 8-bit timer H compare register 10
(CMP10) when starting the timer count operation (TMHE0 = 1) after the timer
count operation was stopped (TMHE0 = 0) (be sure to set again even if setting the
same value to CMP10).
When the internal oscillation clock is selected as the clock to be supplied to the
CPU, the clock of the internal oscillator is divided and supplied as the count clock.
If the count clock is the internal oscillation clock, the operation of 8-bit timer H1 is
not guaranteed (except when CKS12, CKS11, CKS10 = 1, 0, 1 (f
When TMHE1 = 1, setting the other bits of the TMHMD1 register is prohibited.
In the PWM output mode and carrier generator mode, be sure to set 8-bit timer H
compare register 11 (CMP11) when starting the timer count operation (TMHE1 =
1) after the timer count operation was stopped (TMHE1 = 0) (be sure to set again
even if setting the same value to CMP11).
When the carrier generator mode is used, set so that the count clock frequency of
TMH1 becomes more than 6 times the count clock frequency of TM51.
In PWM output mode, three operation clocks (signal selected using the CKSn2 to
CKSn0 bits of the TMHMDn register) are required to transfer the CMP1n register
value after rewriting the register.
Be sure to set the CMP1n register when starting the timer count operation
(TMHEn = 1) after the timer count operation was stopped (TMHEn = 0) (be sure to
set again even if setting the same value to the CMP1n register).
Make sure that the CMP1n register setting value (M) and CMP0n register setting
value (N) are within the following range.
00H ≤ CMP1n (M) < CMP0n (N) ≤ FFH
Do not rewrite the NRZB1 bit again until at least the second clock after it has been
rewritten, or else the transfer from the NRZB1 bit to the NRZ1 bit is not
guaranteed.
When 8-bit timer/event counter 51 is used in the carrier generator mode, an
interrupt is generated at the timing of <1>. When 8-bit timer/event counter 51 is
used in a mode other than the carrier generator mode, the timing of the interrupt
generation differs.
Be sure to set the CMP11 register when starting the timer count operation
(TMHE1 = 1) after the timer count operation was stopped (TMHE1 = 0) (be sure to
set again even if setting the same value to the CMP11 register).
Set so that the count clock frequency of TMH1 becomes more than 6 times the
count clock frequency of TM51.
Set the values of the CMP01 and CMP11 registers in a range of 01H to FFH.
In the carrier generator mode, three operating clocks (signal selected by CKS12 to
CKS10 bits of TMHMD1 register) or more are required from when the CMP11
register value is changed to when the value is transferred to the register.
Be sure to set the RMC1 bit before the count operation is started.
Do not change the count clock and interval time (by setting bits 4 to 7 (WTM4 to
WTM7) of WTM) during watch timer operation.
When operation of the watch timer and 5-bit counter is enabled by the watch timer
mode control register (WTM) (by setting bits 0 (WTM0) and 1 (WTM1) of WTM to
1), the interval until the first interrupt request (INTWT) is generated after the
register is set does not exactly match the specification made with bit 3 (WTM3) of
WTM. This is because there is a delay up to one 11-bit prescaler output cycle
until the 5-bit counter starts counting. Subsequently, however, the INTWT signal
is generated at the specified intervals.
APPENDIX D LIST OF CAUTIONS
User’s Manual U15947EJ3V1UD
Cautions
R
/2
7
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p. 225
p. 225
p. 225
p. 227
p. 227
p. 227
p. 227
p. 233
p. 233
p. 234
p. 239
p. 239
p. 241
p. 241
p. 241
p. 241
p. 241
p. 248
p. 251
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