upd78f0148m1gka1-9eu Renesas Electronics Corporation., upd78f0148m1gka1-9eu Datasheet - Page 374

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upd78f0148m1gka1-9eu

Manufacturer Part Number
upd78f0148m1gka1-9eu
Description
8-bit Single-chip Microcontrollers
Manufacturer
Renesas Electronics Corporation.
Datasheet
374
Address: FF91H
Symbol
(2) Serial status register 0 (CSIS0)
Notes 1.
Caution Be sure to clear bit 7 to 0.
Remarks 1. Figures in parentheses apply to operation with f
CSIS0
This is an 8-bit register used to select the base clock, control the communication operation, and indicate the
status of serial interface CSIA0.
This register can be set by a 1-bit or 8-bit memory manipulation instruction.
RESET input clears this register to 00H. However, rewriting CSIS0 is prohibited when bit 0 (TSF0) is 1.
2.
3.
4.
5.
STBE0
BUSYLV0
2. f
Bits 0 and 1 are read-only.
Set the base clock to satisfy the following conditions.
• V
• V
• V
• V
STBE0 is valid only in master mode.
When STBE0 is set to 1, two transfer clocks are consumed between byte transfers regardless of the
setting of automatic data transfer interval specification register 0 (ADTI0). That is, 10 transfer clocks
are used for 1-byte transfer if ADTI0 = 00H is set.
In bit error detection by busy input, the active level specified by BUSYLV0 is detected.
BUSYE0
CKS00
After reset: 00H
DD
DD
DD
DD
X
0
1
0
1
0
1
7
0
0
1
: X1 input clock oscillation frequency
Notes 3, 4
= 4.0 to 5.5 V: Base clock ≤ 10 MHz
= 3.3 to 4.0 V: Base clock ≤ 8.38 MHz
= 2.7 to 3.3 V: Base clock ≤ 5 MHz
= 2.5 to 2.7 V: Base clock ≤ 2.5 MHz
Note 5
Figure 17-4. Format of Serial Status Register 0 (CSIS0) (1/2)
f
f
Strobe output disabled
Strobe output enabled
Busy signal detection disabled (input via BUSY0 pin is ignored)
Busy signal detection enabled and communication wait by busy signal is executed
Low level
High level
X
X
/2 (5 MHz)
(10 MHz)
CKS00
6
R/W
CHAPTER 17 SERIAL INTERFACE CSIA0
Note 1
STBE0
5
User’s Manual U15947EJ3V1UD
BUSYE0
Busy signal detection enable/disable
Busy signal active level setting
4
Base clock (f
Strobe output enable/disable
X
BUSYLV0
= 10 MHz.
W
3
) selection
Note 2
ERRE0
2
ERRF0
1
TSF0
0

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