AD9251BCPZRL7 Analog Devices, Inc., AD9251BCPZRL7 Datasheet - Page 9

• Manufacturer Part Number: AD9251BCPZRL7
• Description: 14-bit, 20 Msps/40 Msps/65 Msps/80 Msps, 1.8 V Dual Analog-to-digital Converter
• Manufacturer: Analog Devices, Inc.

Preliminary Technical Data
TIMING SPECIFICATIONS
Table 5.
Parameter
SYNC TIMING REQUIREMENTS
SPI TIMING REQUIREMENTS
t
t
t
t
t
t
t
t
t
t
t
SSYNC
HSYNC
DS
DH
CLK
S
H
HIGH
LOW
EN_SDIO
DIS_SDIO
CH A/CH B DATA
DCOA/DCOB
CLK+
CLK–
VIN
Conditions
SYNC to rising edge of CLK setup time
SYNC to rising edge of CLK hold time
Setup time between the data and the rising edge of SCLK
Hold time between the data and the rising edge of SCLK
Period of the SCLK
Setup time between CS and SCLK
Hold time between CS and SCLK
SCLK pulse width high
SCLK pulse width low
Time required for the SDIO pin to switch from an input to an
output relative to the SCLK falling edge
Time required for the SDIO pin to switch from an output to an
input relative to the SCLK rising edge
SYNC
CLK+
N – 1
t
CH
t
Figure 3. CMOS Interleaved Output Timing
Figure 4. SYNC Input Timing Requirements
SSYNC
t
PD
N
t
Rev. Pr A | Page 9 of 36
N – 9
t
CH A
A
CLK
t
DCO
t
SKEW
CH B
N – 9
N + 1
t
HSYNC
CH A
N – 8
CH B
N – 8
N + 2
CH A
N – 7
N + 3
CH B
N – 7
CH A
N – 6
Min
2
2
40
2
2
10
10
10
10
N + 4
CH B
N – 6
CH A
N – 5
Typ
0.24
0.40
N + 5
Max
AD9251
ns
ns
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns