AD9251BCPZRL7 Analog Devices, Inc., AD9251BCPZRL7 Datasheet - Page 32

• Manufacturer Part Number: AD9251BCPZRL7
• Description: 14-bit, 20 Msps/40 Msps/65 Msps/80 Msps, 1.8 V Dual Analog-to-digital Converter
• Manufacturer: Analog Devices, Inc.

AD9251
Addr
(Hex)
0x0E
0x10
0x14
0x15
0x16
0x17
0x18
0x19
0x1A
0x1B
0x1C
0x24
Digital Feature Control
0x100
Register
Name
BIST enable
Offset adjust
(local)
Output mode
output_adjust
output_phase
output_delay
vref
user_patt1_lsb
user_patt1_msb
user_patt2_lsb
user_patt2_msb
misr_lsb
Sync control
Bit 7
(MSB)
Open
8-bit device offset adjustment 7:0 (local)
Offset adjust in LSBs from +127 to −128 (twos complement format)
00 = 3.3 V CMOS
10 = 1.8 V CMOS
3.3 V DCO
Drive Strength
00 = 1 stripe
(default)
01 = 2 stripes
10 = 3 stripes
11 = 4 stripes
DCO
output
polarity
0 =
normal
1 =
inverted
(local)
Enable
DCO
delay
Internal
adjustment [1:0];
00 = 1.25 Vpp
01 = 1.5 Vpp
10 = 1.75 Vpp
11 = 2.0 Vpp
B7
B15
B7
B15
Open
Open
Bit 6
B6
B14
B6
B14
Open
Open
Bit 5
Output MUX
enable
(interleaved)
1.8 V DCO
Drive Strength
00 = 1 stripe (default)
01 = 2 stripes
10 = 3 stripes
11 = 4 stripes
Enable
data
delay
Internal Vref adjustment 2:0;
New digital scheme
000 = 1.0 Vpp
001 = 1.14 Vpp
010 = 1.33 Vpp
011 = 1.60 Vpp
100 = 2.0 Vpp
B5
B13
B5
B13
Open
Open
B4
B12
B4
B12
Open
Open
Bit 4
Output
disable
(local)
Rev. PrH | Page 32 of 36
B3
B11
B3
B11
Open
Open
Bit 3
0111 = one/zero word toggle
1000 = user input
1001 = one/zero bit toggle
1010 = 1x Sync
1011 = one bit high
1100 = Mixed bit frequency
Open
Open
3.3 V Data
Drive Strength
00 = 1 stripe
(default)
01 = 2 stripes
10 = 3 stripes
11 = 4 stripes
Input clock phase adjust [2:0]
(Value is number of input clock
cycles of phase delay)
000 = no delay
001 = 1 input clock cycle
010 = 2 input clock cycles
011 = 3 input clock cycles
100 = 4 input clock cycles
101 = 5 input clock cycles
110 = 6 input clock cycles
111 = 7 input clock cycles
DCO / data delay[2:0]
0 – 0.56 ns
1 – 1.12 ns
…
7 – 4.48 ns
B2
B10
B2
B10
Open
Clock
Bit 2
BIST init
Output
invert
(local)
Bit 1
Open
00 = offset binary
01 = twos
complement
10 = Gray code
11 = offset binary
(local)
1.8 V Data
Drive Strength
00 = 1 stripe
(default)
01 = 2 stripes
10 = 3 stripes
11 = 4 stripes
B1
B9
B1
B9
Open
Clock
Preliminary Technical Data
Bit 0
(LSB)
B0
B8
B0
B8
B0
Master
BIST
enable
0x00
Default
Value
(Hex)
0x00
0x00
0x00
0x22
0x00
0x00
0xE0
0x00
0x00
0x00
0x00
0x01
Comments
When bit 0 is set,
the BIST function
is initiated
Device offset trim
Configures the
outputs and the
format of the data
Determines
CMOS output
drive strength
properties
On devices that
utilize global clock
divide, determines
which phase of
the divider output
is used to supply
the output clock;
internal latching is
unaffected
This sets the fine
output delay of
the output clock
but does not
change internal
timing
Select and/or
adjustments the
Vref
User defined
pattern 1 LSB
User defined
pattern 1 MSB
User defined
pattern 2 LSB
User defined
pattern 2 MSB
Least significant
byte of MISR; read
only