AD9251BCPZRL7 Analog Devices, Inc., AD9251BCPZRL7 Datasheet - Page 26

• Manufacturer Part Number: AD9251BCPZRL7
• Description: 14-bit, 20 Msps/40 Msps/65 Msps/80 Msps, 1.8 V Dual Analog-to-digital Converter
• Manufacturer: Analog Devices, Inc.

AD9251
BUILT-IN SELF-TEST (BIST) AND OUTPUT TEST
The AD9251 includes built-in test features designed to enable
verification of the integrity of each channel as well as facilitate
board level debugging. A built-in self-test (BIST) feature that
verifies the integrity of the digital datapath of the AD9251 is
included. Various output test options are also provided to place
predictable values on the outputs of the AD9251.
BUILT-IN SELF-TEST (BIST)
The BIST is a thorough test of the digital portion of the selected
AD9251 signal path. Perform the BIST test after a reset to ensure
the part is in a known state. During BIST, data from an internal
pseudorandom noise (PN) source is driven through the digital
datapath of both channels starting at the ADC block output. At
the datapath output, CRC logic calculates a signature from the
data. The BIST sequence runs for 512 cycles and stops. Once
completed, the BIST compares the signature results against a pre-
determined value. If the signatures matches, the BIST sets Bit 0 of
Register 0x24 signifying the test passed. If the BIST test failed, Bit
0 of Register 0x24 is cleared. The outputs are not disconnected
during this test, so the PN sequence can be observed as it runs.
Writing the value 0x05 to Register 0x0E runs the BIST. This enables
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the BIST (Bit 0) and resets the PN sequence generator (Bit 2). At
the completion of the BIST, Bit 0 of Register 0x24 is automatically
cleared. The PN sequence can be continued from its last value
by writing a 0 in Bit 2 in Register 0x0E. However, if the PN
sequence is not reset, the signature calculation will not equal
the pre-determined value at the end of the test. The user would
need to rely on verifying the output data at that point.
OUTPUT TEST MODES
The output test options are shown in Figure X. When an output
test mode is enabled, the analog section of the ADC is discon-
nected from the digital back end blocks and the test pattern is
run through the output formatting block. Some of the test
patterns are subject to output formatting, and some are not. The
PN generators from the PN sequence tests can be reset by
setting Bit 4 or Bit 5 of Register 0x0D. These tests can be
performed with or without an analog signal (if present, the
analog signal is ignored), but they do require an encode clock.
For more information, see the AN-877 Application Note,
Interfacing to High Speed ADCs via SPI.
Preliminary Technical Data