AD9251BCPZRL7 Analog Devices, Inc., AD9251BCPZRL7 Datasheet - Page 33

• Manufacturer Part Number: AD9251BCPZRL7
• Description: 14-bit, 20 Msps/40 Msps/65 Msps/80 Msps, 1.8 V Dual Analog-to-digital Converter
• Manufacturer: Analog Devices, Inc.

Preliminary Technical Data
Addr
(Hex)
0x101
MEMORY MAP REGISTER DESCRIPTIONS
For additional information about functions controlled in
Register 0x00 to Register 0xFF, see the AN-877 Application Note,
Interfacing to High Speed ADCs via SPI.
Sync Control (Register 0x100)
Bits[7:3]—Reserved
Bit 2—Clock Divider Next Sync Only
If the master sync enable bit (Address 0x100, Bit 0) and the
clock divider sync enable bit (Address 0x100, Bit 1) are high, Bit
2 allows the clock divider to sync to the first sync pulse it receives
Register
Name
(global)
usr2
Bit 7
(MSB)
Enable
OE
Pin 31
(local)
Bit 6
Reserved [6:0] = 0
Bit 5
Bit 4
Rev. PrH | Page 33 of 36
Bit 3
and to ignore the rest. The clock divider sync enable bit
(Address 0x100, Bit 1) resets after it syncs.
Bit 1—Clock Divider Sync Enable
Bit 1 gates the sync pulse to the clock divider. The sync signal is
enabled when Bit 1 is high and Bit 0 is high. This is continuous
sync mode.
Bit 0—Master Sync Enable
Bit 0 must be high to enable any of the sync functions. If the
sync capability is not used this bit should remain low to
conserve power.
divider
next sync
only
Bit 2
Bit 1
divider
sync
enable
Bit 0
(LSB)
sync
enable
Default
Value
(Hex)
0x80
Comments
AD9251