AD9251BCPZRL7 Analog Devices, Inc., AD9251BCPZRL7 Datasheet - Page 25

• Manufacturer Part Number: AD9251BCPZRL7
• Description: 14-bit, 20 Msps/40 Msps/65 Msps/80 Msps, 1.8 V Dual Analog-to-digital Converter
• Manufacturer: Analog Devices, Inc.

Preliminary Technical Data
When using the SPI interface, the data outputs and DCO of
each channel can be independently three-stated by using the
output enable bar bit in Register 0x14. {Is this Bit 5 in Register
0x14?}
TIMING
The AD9251 provides latched data with a pipeline delay of
9 clock cycles. Data outputs are available one propagation delay
(t
Minimize the length of the output data lines and loads placed
on them to reduce transients within the AD9251. These
transients can degrade converter dynamic performance.
Table 12. Output Data Format
Input (V)
VIN+ − VIN−
VIN+ − VIN−
VIN+ − VIN−
VIN+ − VIN−
VIN+ − VIN−
PD
) after the rising edge of the clock signal.
Condition (V)
< −VREF − 0.5 LSB
= −VREF
= 0
= +VREF − 1.0 LSB
> +VREF − 0.5 LSB
Offset Binary Output Mode
00 0000 0000 0000
00 0000 0000 0000
10 0000 0000 0000
11 1111 1111 1111
11 1111 1111 1111
Rev. PrH | Page 25 of 36
The lowest typical conversion rate of the AD9251 is 2 MSPS. At
clock rates below 2 MSPS, dynamic performance can degrade.
Data Clock Output (DCO)
The AD9251 provides two data clock output (DCO) signals
intended for capturing the data in an external register. In CMOS
output mode, the data outputs are valid on the rising edge of
DCO, unless the DCO clock polarity has been changed via the
SPI. See Figure X for a graphical timing description.
Twos Complement Mode
10 0000 0000 0000
10 0000 0000 0000
00 0000 0000 0000
01 1111 1111 1111
01 1111 1111 1111
AD9251
OR
1
0
0
0
1