AD9251BCPZRL7 Analog Devices, Inc., AD9251BCPZRL7 Datasheet - Page 31

• Manufacturer Part Number: AD9251BCPZRL7
• Description: 14-bit, 20 Msps/40 Msps/65 Msps/80 Msps, 1.8 V Dual Analog-to-digital Converter
• Manufacturer: Analog Devices, Inc.

Preliminary Technical Data
MEMORY MAP REGISTER TABLE
All address and bit locations that are not included in Table 16 are not currently supported for this device.
Table 16.
Addr
(Hex)
Chip Configuration Registers
0x00
0x01
0x02
Device Index and Transfer Registers
0x05
0xFF
Program Registers (May or May Not Be Indexed by Device Index)
0x08
0x09
0x0B
0x0D
Register
Name
SPI port
configuration
(global)
Chip ID (global)
Chip grade
(global)
Channel index
Transfer
Modes
Clock (global)
Clock divide
(global)
Test mode (local)
Bit 7
(MSB)
0
8-bit CHIP ID Bits [7:0]
AD9251 = 0x23
Open
Open
Open
External
power
down
enable
(local)
Open
Open
User test mode
(local)
00 = single
01 = alternate
10 = single once
11 = alternate
once
Bit 6
LSB
first
Speed Grade ID 6:4
20 Msps = 000
40 Msps = 001
65 Msps = 010
80 Msps = 011
Open
Open
External pin function
0x00 full power
down
0x01 standby
(local)
Open
Bit 5
Soft reset
Open
Open
Reset PN
long gen
Open
Bit 4
1
Open
Open
Open
Reset PN
short gen
Open
Rev. PrH | Page 31 of 36
Bit 3
1
Open
Open
Open
Open
Output test mode [3:0] (local)
0000 = off (default)
0001 = midscale short
0010 = positive FS
0011 = negative FS
0100 = alternating checkerboard
0101 = PN 23 sequence
0110 = PN 9 sequence
Bit 2
Soft
reset
Open
Open
Clock divider [2:0]
Clock divide ratio
000 = divide by 1
001 = divide by 2
010 = divide by 3
011 = divide by 4
100 = divide by 5
101 = divide by 6
110 = divide by 7
111 = divide by 8
Open
Bit 1
LSB first
ADC B
default
0 = chip run
1 = full power down
2 = standby
3 = chip wide digital
reset
(local)
Open
Bit 0
(LSB)
0
Transfer
ADC A
default
Duty
cycle
stabilize
Default
Value
(Hex)
0x18
Read
only
Read
only
0xFF
0x00
0x80
0x01
0x00
0x00
Comments
The nibbles are
mirrored so that
LSB or MSB first
mode will register
correctly, regard-
less of shift mode
Unique chip ID
used to diffe-
rentiate devices;
read only
Unique speed
grade ID used to
differentiate
devices; read only
Bits are set to
determine which
device on chip
receives the next
write command;
the default is all
devices on chip
Synchronously
transfers data
from the master
shift register to
the slave
Determines
various generic
modes of chip
operation
The divide ratio is
the value plus 1
When set, the test
data is placed on
the output pins in
place of normal
data
AD9251