AD9251BCPZRL7 Analog Devices, Inc., AD9251BCPZRL7 Datasheet - Page 30

• Manufacturer Part Number: AD9251BCPZRL7
• Description: 14-bit, 20 Msps/40 Msps/65 Msps/80 Msps, 1.8 V Dual Analog-to-digital Converter
• Manufacturer: Analog Devices, Inc.

AD9251
MEMORY MAP
READING THE MEMORY MAP REGISTER TABLE
Each row in the memory map register table (see Table 16) has
eight bit locations. The memory map is roughly divided into
four sections: the chip configuration registers (Address 0x00 to
Address 0x02); the channel index and transfer registers
(Address 0x05 and Address 0xFF); the ADC functions registers,
including setup, control, and test (Address 0x08 to Address
0x25); and the digital feature control registers (Address 0x100 to
Address 0x11B).
The memory map register table (see Table 16) documents the
default hexadecimal value for each hexadecimal address shown.
The column with the heading Bit 7 (MSB) is the start of the
default hexadecimal value given. For example, Address 0x18, the
vref register, has a hexadecimal default value of 0xc0. This means
that Bit 7 = 1, Bit 6 = 1, and the remaining bits are 0s. This
setting is the default reference selection setting. The default
value uses a 2.0 v p-p reference. For more information on this
function and others, see the AN-877 Application Note, Interfacing
to High Speed ADCs via SPI. This document details the functions
controlled by Register 0x00 to register 0xff. The remaining
registers, from Register 0x100 to Register 0x11b, are
documented in the Memory Map section.
OPEN LOCATIONS
All address and bit locations that are not included in the SPI
map are not currently supported for this device. Unused bits of
a valid address location should be written with 0s. Writing to these
locations is required only when part of an address location is
open (for example, Address 0x18). If the entire address location
is open (for example, Address 0x13), this address location should
not be written.
DEFAULT VALUES
After the AD9251 is reset, critical registers are loaded with
default values. The default values for the registers are given in
the memory map register table (see Table 16).
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Logic Levels
An explanation of logic level terminology follows:
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Transfer Register Map
Address 0x08 to Address 0x18 are shadowed. Writes to these
addresses do not affect part operation until a transfer command
is issued by writing 0x01 to Address 0xFF, setting the transfer bit.
This allows these registers to be updated internally and simulta-
neously when the transfer bit is set. The internal update takes
place when the transfer bit is set, and the bit autoclears.
Channel-Specific Registers
Some channel setup functions can be programmed differently
for each channel. In these cases, channel address locations are
internally duplicated for each channel. These registers and bits
are designated in the memory map register table as local. These
local registers and bits can be accessed by setting the appropriate
Channel A or Channel B bits in Register 0x05If both bits are set,
the subsequent write affects the registers of both channels. In a
read cycle, set only Channel A or Channel B to read one of the
two registers. If both bits are set during an SPI read cycle, the
part returns the value for Channel A. Registers and bits
designated as global in the memory map register table affect the
entire part or the channel features for which independent settings
are not allowed between channels. The settings in Register 0x05
do not affect the global registers and bits.
“Bit is set” is synonymous with “bit is set to Logic 1” or
“writing Logic 1 for the bit. ”
“Clear a bit” is synonymous with “bit is set to Logic 0” or
“writing Logic 0 for the bit. ”
Preliminary Technical Data