AD9251BCPZRL7 Analog Devices, Inc., AD9251BCPZRL7 Datasheet - Page 2

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AD9251BCPZRL7

Manufacturer Part Number
AD9251BCPZRL7
Description
14-bit, 20 Msps/40 Msps/65 Msps/80 Msps, 1.8 V Dual Analog-to-digital Converter
Manufacturer
Analog Devices, Inc.
Datasheet
AD9251
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagram .............................................................. 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
General Description ......................................................................... 3
Specifications ..................................................................................... 4
Absolute Maximum Ratings .......................................................... 10
Pin Configuration and Function Descriptions ........................... 11
Typical Performance Characteristics ........................................... 13
Equivalent Circuits ......................................................................... 16
Theory of Operation ...................................................................... 18
REVISION HISTORY
x/09—Revision 0: Initial Version
DC Specifications ......................................................................... 4
AC Specifications .......................................................................... 5
Digital Specifications ................................................................... 7
Switching Specifications .............................................................. 8
Timing Specifications .................................................................. 9
Thermal Characteristics ............................................................ 10
ESD Caution ................................................................................ 10
ADC Architecture ...................................................................... 18
Analog Input Considerations.................................................... 18
Voltage Reference ....................................................................... 21
Rev. PrH | Page 2 of 36
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
Built-In Self-Test (BIST) and Output Test .................................. 26
Channel/Chip Synchronization .................................................... 27
Serial Port Interface (SPI) .............................................................. 28
Memory Map .................................................................................. 30
Applications Information .............................................................. 34
Outline Dimensions ....................................................................... 35
Clock Input Considerations ...................................................... 22
Power Dissipation and Standby Mode .................................... 24
Digital Outputs ........................................................................... 24
Timing ......................................................................................... 25
Built-In Self-Test (BIST) ............................................................ 26
Output Test Modes ..................................................................... 26
Configuration Using the SPI ..................................................... 28
Hardware Interface ..................................................................... 28
Configuration Without the SPI ................................................ 29
SPI Accessible Features .............................................................. 29
Reading the Memory Map Register Table ............................... 30
Open Locations .......................................................................... 30
Memory Map Register Table ..................................................... 31
Memory Map Register Descriptions ........................................ 33
Design Guidelines ...................................................................... 34
Ordering Guide .......................................................................... 35
Preliminary Technical Data
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 

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