IDT72T54252L6-7BB IDT, Integrated Device Technology Inc, IDT72T54252L6-7BB Datasheet - Page 9

• Manufacturer Part Number: IDT72T54252L6-7BB
• Description: IC FIFO DDR/SDR QUAD/DUAL 324BGA
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 72Tr

Specifications of IDT72T54252L6-7BB

• Function: Asynchronous
• Memory Size: 20K (1K x 20)
• Access Time: 3.8ns
• Voltage - Supply: 2.375 V ~ 2.625 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 324-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Data Rate: -
• Other names: 72T54252L6-7BB

PIN DESCRIPTIONS (CONTINUED)
NOTES:
1. All unused outputs may be left floating.
2. All CMOS pins should remain unchanged. CMOS format means that the pin is intended to be tied directly to V
3. These pins are for the JTAG port. Please refer to pages 27-31 and Figures 7-9.
IDT72T54242/72T54252/72T54262 2.5V QUAD/DUAL TeraSync
32K x 10 x 4/16K x 20 x 2, 64K x 10 x 4/32K x 20 x 2 and 128K x 10 x 4/64K x 20 x 2
TCK
TDI
TDO
TMS
TRST
WCLK0/1/2/3
WCS0/1/2/3
WDDR
WEN0/1/2/3
V
V
GND
Vref
DDQ
CC
Symbol
(3)
(3)
(3)
(3)
(3)
Write Chip Select
JTAG Clock
JTAG Test Data
Input
JTAG Test Data
Output
JTAG Mode Select
JTAG Reset
Write Clock 0/1/2/3
Write Port DDR
Write Enable 0/1/2/3 HSTL-LVTTL These are the write enable inputs corresponding to each of the four FIFOs on the write port. In SDR,
+2.5V Supply
Output Rail Voltage
Ground Pin
Reference voltage
Name
HSTL-LVTTL Clock input for JTAG function. One of four terminals required by IEEE Standard 1149.1-1990. Test
HSTL-LVTTL One of four terminals required by IEEE Standard 1149.1-1990. During the JTAG boundary scan
HSTL-LVTTL One of four terminals required by IEEE Standard 1149.1-1990. During the JTAG boundary scan
HSTL-LVTTL TMS is a serial input pin. One of four terminals required by IEEE Standard 1149.1-1990. TMS directs
HSTL-LVTTL TRST is an asynchronous reset pin for the JTAG controller. The JTAG TAP controller does not
HSTL-LVTTL These are the clock inputs corresponding to each of the four FIFOs on the write port. If Dual mode
HSTL-LVTTL These are the write chip select inputs corresponding to each of the four FIFOs on the write port. This
I/O Type
OUTPUT
CMOS
Ground
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
Power
Power
Power
(2)
operations of the device are synchronous to TCK. Data from TMS and TDI are sampled on the
rising edge of TCK and outputs change on the falling edge of TCK. If the JTAG function is not used
this signal needs to be tied to GND.
operation, test data serially loaded via the TDI on the rising edge of TCK to either the Instruction
Register, ID Register and Bypass Register. An internal pull-up resistor forces TDI HIGH if left
unconnected.
operation, test data serially loaded output via the TDO on the falling edge of TCK from either the
Instruction Register, ID Register and Bypass Register. This output is high impedance except
when shifting, while in SHIFT-DR and SHIFT-IR controller states.
the device through its TAP controller states. An internal pull-up resistor forces TMS HIGH if left
unconnected.
automatically reset upon power-up, thus it must be reset by either this signal or by setting TMS= HIGH
for five TCK cycles. If the TAP controller is not properly reset then the FIFO outputs will always be
in high-impedance. If the JTAG function is used but the user does not want to use TRST, then TRST
can be tied with MRS to ensure proper FIFO operation. If the JTAG function is not used then this signal
needs to be tied to GND. An internal pull-up resistor forces TRST HIGH if left unconnected.
is selected then WCLK1 and WCLK3 are not used and should be tied to GND. In SDR mode data
will be written on the rising edge of WCLK when WEN and WCS are LOW at the rising edge of WCLK.
In DDR mode data will be written on both rising and falling edge of WCLK when WEN and WCS are
LOW at the rising edge of WCLK.
pin can be regarded as a second write enable input, enabling/disabling write operations. WCS is
only sampled on the rising edge of WCLK. If Dual mode is selected then WCS1 and WCS3 are not
used and should be tied to V
During master reset, this pin selects the input port to operate in DDR or SDR format. If WDDR is HIGH,
then a word is written on the rising and falling edge of the appropriate WCLK0, 1, 2 and 3 input.
If WDDR is LOW, then a word is written only on the rising edge of the appropriate WCLK0, 1, 2 and
3 inputs.
when this signal (and WCS) are LOW data on the databus will be written into the FIFO memory on
every rising edge of WCLK. In DDR mode, data will be written on both rising and falling edges of
WCLK. Note in DDR mode the WEN and WCS are only sampled on the rising edge of WCLK. New
data will always begin writing from the rising edge, not the falling edge of WCLK. If Dual mode is
selected then WEN1 and WEN3 are not used and should be tied to V
These are V
This pin should be tied to the desired voltage rail for providing to the output drivers. Nominally 1.5V
or 1.8V for HSTL, 2.5V for LVTTL.
These ground pins are for the core device and must be connected to the GND rail.
This is a Voltage Reference input and must be connected to a voltage level determined in the Voltage
Recommended DC Operating Conditions section. This provides the reference voltage when using
HSTL class inputs. If HSTL class inputs are not being used, this pin must be connected to GND.
CC
core power supply pins and must all be connected to a +2.5V supply rail.
™
9
DDR/SDR FIFO
CC
.
Description
CC
or GND and these particular pins are not tested for V
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
CC
.
FEBRUARY 11, 2009
IH
or V
IL
.