IDT72T54252L6-7BB IDT, Integrated Device Technology Inc, IDT72T54252L6-7BB Datasheet - Page 29

• Manufacturer Part Number: IDT72T54252L6-7BB
• Description: IC FIFO DDR/SDR QUAD/DUAL 324BGA
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 72Tr

Specifications of IDT72T54252L6-7BB

• Function: Asynchronous
• Memory Size: 20K (1K x 20)
• Access Time: 3.8ns
• Voltage - Supply: 2.375 V ~ 2.625 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 324-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Data Rate: -
• Other names: 72T54252L6-7BB

JTAG TIMING SPECIFICATIONS
(IEEE 1149.1 COMPLIANT)
Test Access Port (IEEE 1149.1) specifications. Five additional pins (TDI, TDO,
TMS, TCK and TRST) are provided to support the JTAG boundary scan
interface. Note that IDT provides appropriate Boundary Scan Description
Language program files for these devices.
TEST ACCESS PORT (TAP)
internal JTAG state machine. It consists of four input ports (TCLK, TMS, TDI,
TRST) and one output port (TDO).
IDT72T54242/72T54252/72T54262 2.5V QUAD/DUAL TeraSync
32K x 10 x 4/16K x 20 x 2, 64K x 10 x 4/32K x 20 x 2 and 128K x 10 x 4/64K x 20 x 2
The JTAG test port in this device is fully compliant with the IEEE Standard
The TAP interface is a general-purpose port that provides access to the
All inputs
Eg: Dins, Clks
(BSDL file
describes the
chain order)
TDI
TMS
TCK
TRST
TAP
In Pad
In Pad
Incell
Incell
Figure 8. JTAG Architecture
Instruction
Register
Bypass
Instruction
Select
Enable
Core
Logic
ID
™
29
DDR/SDR FIFO
complete description refer to the IEEE Standard Test Access Port Specification
(IEEE Std. 1149.1-1990).
THE TAP CONTROLLER
TMS and TCLK signals to generate clock and control signals to the Instruction
and Data Registers for capture and updating of data passed through the TDI
serial input.
The Standard JTAG interface consists of five basic elements:
•
•
•
•
•
The following sections provide a brief description of each element. For a
The Figure below shows the standard Boundary-Scan Architecture
The TAP controller is a synchronous finite state machine that responds to
Outcell
Outcell
Test Access Port (TAP)
TAP controller
Instruction Register (IR)
Data Register Port (DR)
Bypass Register (BYR)
Out Pad
Out Pad
COMMERCIAL AND INDUSTRIAL
All outputs
TEMPERATURE RANGES
FEBRUARY 11, 2009
6158 drw13
TDO