IDT72T54252L6-7BB IDT, Integrated Device Technology Inc, IDT72T54252L6-7BB Datasheet - Page 27

• Manufacturer Part Number: IDT72T54252L6-7BB
• Description: IC FIFO DDR/SDR QUAD/DUAL 324BGA
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 72Tr

Specifications of IDT72T54252L6-7BB

• Function: Asynchronous
• Memory Size: 20K (1K x 20)
• Access Time: 3.8ns
• Voltage - Supply: 2.375 V ~ 2.625 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 324-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Data Rate: -
• Other names: 72T54252L6-7BB

is asserted LOW on the LOW-to-HIGH transitions of the Write Clock (WCLK).
PAF is reset to HIGH on the LOW-to-HIGH transitions of the Read Clock (RCLK).
See Figure 31 and 33, Synchronous and Asynchronous Programmable
Almost-Full Flag Timing (IDT Standard and FWFT mode), for the relevant timing
information.
ECHO READ CLOCK (ERCLK0/1/2/3)
device, each corresponding to their respective input read clocks in the FIFO.
The echo read clock is a free-running clock output, that will always follow the
RCLK input regardless of the read enables and read chip selects. The ERCLK
output follows the RCLK input with an associated delay. This delay provides the
user with a more effective read clock source when reading data from the output
bus. This is especially helpful at high speeds when variables within the device
may cause changes in the data access times. These variations in access time
may be caused by ambient temperature, supply voltage, or device characteristics.
effect on the echo read clock output produced by the FIFO, therefore the echo
read clock output level transitions should always be at the same position in time
relative to the data outputs. Note, that echo read clock is guaranteed by design
to be slower than the slowest data outputs. Refer to Figure 6, Echo Read Clock
and Data Output Relationship, Figures 25, 26, and 27 Echo Read Clock and
Read Enable Operation for timing information. Each echo read clock output
operate independently of the others and transitions with respect to the data
outputs of its FIFO.
Q
NOTES:
1. REN is LOW.
2. t
3. Qslowest is the data output with the slowest access time, t
4. Time, t
IDT72T54242/72T54252/72T54262 2.5V QUAD/DUAL TeraSync
32K x 10 x 4/16K x 20 x 2, 64K x 10 x 4/32K x 20 x 2 and 128K x 10 x 4/64K x 20 x 2
SLOWEST
Each programmable almost full flag operates independently of the others.
There are four echo read clock outputs (two in Dual mode) available in this
Any variations effecting the data access time will also have a corresponding
ERCLK
ERCLK
RCLK
Figure 6. Echo Read Clock and Data Output Relationship
(3)
> t
D
is greater than zero, guaranteed by design.
A
, guaranteed by design.
t
A
t
ERCLK
t
D
A
.
6158 drw11
™
27
DDR/SDR FIFO
TABLE 6 — T
Configuration
DDR Output
DDR Output
SDR Output
SDR Output
DDR Input
DDR Input
SDR Input
SDR Input
Data Port
to
to
to
to
Status Flags
EF/OR
EF/OR
EF/OR
EF/OR
FF/IR
FF/IR
FF/IR
FF/IR
PAE
PAF
PAE
PAF
PAE
PAF
PAE
PAF
SKEW
Negative Edge WCLK to
Negative Edge RCLK to
Negative Edge WCLK to
Negative Edge RCLK to
Negative Edge WCLK to
Negative Edge WCLK to
Negative Edge RCLK to
Negative Edge RCLK to
Positive Edge RCLK to
Positive Edge RCLK to
Positive Edge WCLK to
Positive Edge WCLK to
Positive Edge WCLK to
Positive Edge RCLK to
Positive Edge WCLK to
Positive Edge RCLK to
T
Positive Edge WCLK
Positive Edge WCLK
Positive Edge WCLK
Positive Edge WCLK
Positive Edge WCLK
Positive Edge WCLK
Positive Edge WCLK
Positive Edge WCLK
Positive Edge RCLK
Positive Edge RCLK
Positive Edge RCLK
Positive Edge RCLK
Positive Edge RCLK
Positive Edge RCLK
Positive Edge RCLK
Positive Edge RCLK
SKEW
MEASUREMENT
COMMERCIAL AND INDUSTRIAL
Measurement
TEMPERATURE RANGES
FEBRUARY 11, 2009
Parameter
Datasheet
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
SKEW2
SKEW2
SKEW3
SKEW3
SKEW2
SKEW1
SKEW3
SKEW3
SKEW1
SKEW2
SKEW3
SKEW3
SKEW1
SKEW1
SKEW3
SKEW3