IDT72T54252L6-7BB IDT, Integrated Device Technology Inc, IDT72T54252L6-7BB Datasheet - Page 35

• Manufacturer Part Number: IDT72T54252L6-7BB
• Description: IC FIFO DDR/SDR QUAD/DUAL 324BGA
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 72Tr

Specifications of IDT72T54252L6-7BB

• Function: Asynchronous
• Memory Size: 20K (1K x 20)
• Access Time: 3.8ns
• Voltage - Supply: 2.375 V ~ 2.625 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 324-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Data Rate: -
• Other names: 72T54252L6-7BB

WCLK0
NOTES:
1. The timing diagram shown is for FIFO0. FIFO1-3 exhibits the same behavior.
2. t
3. OE0 = LOW, and WCS0 = LOW.
4. WCLK0 must be free running for FF0 to update.
5.
RCLK0
IDT72T54242/72T54252/72T54262 2.5V QUAD/DUAL TeraSync
32K x 10 x 4/16K x 20 x 2, 64K x 10 x 4/32K x 20 x 2 and 128K x 10 x 4/64K x 20 x 2
WEN0
RCS0
REN0
Q[9:0]
D[9:0]
the rising edge of the RCLK0 and the rising edge of the WCLK0 is less than t
measurement).
SKEW1
FF0
MD
1
is the minimum time between a rising RCLK0 edge and a rising WCLK0 edge to guarantee that FF0 will go HIGH (after one WCLK0 cycle plus t
D/C
IW
t
t
ENS
ENS
t
RCSLZ
t
D/C
SKEW1
OW
Figure 12. Write Cycle and Full Flag Timing (Quad mode, IDT Standard mode, SDR to SDR)
(2)
WDDR
0
t
ENH
t
A
1
RDDR
NO WRITE
0
FWFT/SI
0
2
t
WFF
t
DS
t
CLKH
W
SKEW1
X
t
™
WFF
, then the FF0 deassertion may be delayed one extra WCLK0 cycle. (See Table 6 - T
35
DATA READ
DDR/SDR FIFO
t
DH
t
CLK
t
CLKL
t
ENS
t
SKEW1
(2)
t
ENH
t
A
1
NO WRITE
COMMERCIAL AND INDUSTRIAL
2
TEMPERATURE RANGES
NEXT DATA READ
FEBRUARY 11, 2009
t
WFF
t
DS
WFF
). If the time between
W
X+1
6158 drw17
t
DH
t
WFF
SKEW