IDT72T54252L6-7BB IDT, Integrated Device Technology Inc, IDT72T54252L6-7BB Datasheet - Page 14

• Manufacturer Part Number: IDT72T54252L6-7BB
• Description: IC FIFO DDR/SDR QUAD/DUAL 324BGA
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 72Tr

Specifications of IDT72T54252L6-7BB

• Function: Asynchronous
• Memory Size: 20K (1K x 20)
• Access Time: 3.8ns
• Voltage - Supply: 2.375 V ~ 2.625 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 324-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Data Rate: -
• Other names: 72T54252L6-7BB

AC ELECTRICAL CHARACTERISTICS
(Commercial: V
NOTES:
1. With exception to clock cycle frequency, these parameters apply to both DDR and SDR modes of operation.
2. All AC timings apply to both IDT Standard mode and FWFT mode in both Quad and Dual mode.
3. Pulse width less than the minimum value is not allowed.
4. Values guaranteed by design, not currently tested.
5. Industrial temperature range product for the 6-7ns speed grade is available as a standard device. All other speed grades available by special order.
IDT72T54242/72T54252/72T54262 2.5V QUAD/DUAL TeraSync
32K x 10 x 4/16K x 20 x 2, 64K x 10 x 4/32K x 20 x 2 and 128K x 10 x 4/64K x 20 x 2
Symbol
f
f
t
t
t
t
t
t
t
t
t
t
t
f
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
A
ASO
OE
PAES
PAEA
S1
S2
CLK1
CLK2
CLKH1
CLKH2
CLKL1
CLKL2
DS
DH
ENS
ENH
C
SCLK
SCKH
SCKL
SDS
SDH
SENS
SENH
RS
RSS
RSR
RSF
OLZ
OHZ
RCSLZ
RCSHZ
PDLZ
PDHZ
PDL
PDH
WFF
REF
PAFS
PAFA
ERCLK
CLKEN
SKEW1
SKEW2
SKEW3
(3)
(OE - Qn)
CC
Output Enable to Output in Low-Impedance
Clock Cycle Frequency (WCLK & RCLK) SDR
Clock Cycle Frequency (WCLK & RCLK) DDR
Data Access Time
Clock Cycle Time SDR
Clock Cycle Time DDR
Clock High Time SDR
Clock High Time DDR
Clock Low Time SDR
Clock Low Time DDR
Data Setup Time
Data Hold Time
Enable Setup Time
Enable Hold Time
Clock Cycle Frequency (SCLK)
Serial Output Data Access Time
Serial Clock Cycle
Serial Clock High
Serial Clock Low
Serial Data In Setup
Serial Data In Hold
Serial Enable Setup
Serial Enable Hold
Reset Pulse Width
Reset Setup Time
Reset Recovery Time
Reset to Flag and Output Time
Output Enable to Output in High-Impedance
Output Enable to Data Output Valid
RCLK to Active from High-Impedance
RCLK to High-Impedance
Power Down to Output Low-Impedance
Power Down to Output High-Impedance
Power Down LOW
Power Down HIGH
Write Clock to FF or IR
Read Clock to EF or OR
Write Clock to Synchronous Programmable Almost-Full Flag
Read Clock to Synchronous Programmable Almost-Empty Flag
Write Clock to Asynchronous Programmable Almost-Full Flag
Read Clock to Asynchronous Programmable Almost-Empty Flag
RCLK to Echo RCLK Output
RCLK to Echo REN Output
SKEW time between RCLK and WCLK for EF/OR and FF/IR for SDR inputs and outputs
SKEW time between RCLK and WCLK for EF/OR and FF/IR in for DDR inputs and outputs
SKEW time between RCLK and WCLK for PAE and PAF
= 2.5V ± 0.15V, T
A
= 0°C to +70°C;Industrial: V
Parameter
CC
= 2.5V ± 0.15V, T
(1)
™
14
DDR/SDR FIFO
A
= -40°C to +85°C; JEDEC JESD8-A compliant)
Min.
100
200
0.6
2.3
4.5
2.3
4.5
1.5
0.5
1.5
0.5
0.6
0.6
0.6
IDT72T54242L5
IDT72T54252L5
IDT72T54262L5
—
—
10
—
—
45
45
15
15
10
—
—
—
—
—
—
—
—
—
—
—
—
—
—
5
5
5
5
1
4
5
5
Commerical
Max.
19.4
13.5
19.4
200
100
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
4.0
3.6
COMMERCIAL AND INDUSTRIAL
10
20
12
10
10
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
TEMPERATURE RANGES
Min.
IDT72T54242L6-7
IDT72T54252L6-7
IDT72T54262L6-7
100
200
0.6
6.7
2.8
6.0
2.8
6.0
2.0
0.5
2.0
0.5
0.8
0.8
0.8
—
—
13
—
—
45
45
15
15
10
—
—
—
—
—
—
—
—
—
—
—
—
—
—
5
5
5
1
5
6
6
Com'l & Ind'l
FEBRUARY 11, 2009
Max.
19.6
13.7
19.6
150
3.8
3.8
3.8
3.8
3.8
3.8
3.8
3.8
3.8
3.8
4.3
3.8
75
—
—
—
10
20
—
—
—
15
12
12
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Unit
MHz
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns