AN2826 Freescale Semiconductor / Motorola, AN2826 Datasheet - Page 7

• Manufacturer Part Number: AN2826
• Description: DDR-SDRAM Layout Considerations for MCF547x/8x Processors
• Manufacturer: Freescale Semiconductor / Motorola

For further details of the SDRAM controller, please refer to the Reference Manuals available for either the
MCF547x or MCF548x microprocessor families. See
2.2
Due to the critical timing required by DDR SDRAM, there are a number of considerations that should be
taken into account during PCB layout:
Freescale Semiconductor
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Minimize overall trace lengths between the MPU and DDR SDRAM. Trace lengths should be
kept < 6 inches (15cm) if possible. NOTE: the layout of this particular board was constrained by
the fact that a SMT socket was used on the first of these boards to validate first silicon
functionality. As a result, the nearest tall components had to be at least 1.5” or 4 cm from the
center of the footprint for the MCF547x/8x processor. In an embedded system without this
constraint, the components could and should be placed as close as possible to the MPU,
particularly the DDR SDRAM components.
Each DQS, DM, and DQ group of signal traces must have identical loading and similar routing to
maintain timing and signal integrity.
Control and clock signals are routed point-to-point.
Trace length for clock, address, and command signals should match to within +/- 1.25cm
(500mil).
Route DDR signals on layers adjacent to a ground plane, to minimize noise.
Use a VREF plane under the SDRAM.
Layout Guidelines
MCF547X/8X
DDR-SDRAM Layout Considerations for MCF547x/8x Processors, Rev. 1
Figure 4. MCF547X/8X Connections to DDR SDRAM
SDADDR[12:0]
SDDATA[31:0]
SDDQS[3:0]
SD_CLK[1:0]
SD_CLK[1:0]
SDDM[3:0]
SDBA[1:0]
SD_CKE
SDCSn
SDWE
RAS
CAS
Section 5,
“References.”
BA[1:0]
DM[3:0]
DQS[3:0]
DQ[31:0]
RAS
CAS
CLK
CLK
CKE
A[12:0]
CS
WE
DDR SDRAM
DDR SDRAM Overview
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