AN2826 Freescale Semiconductor / Motorola, AN2826 Datasheet - Page 5

AN2826

Manufacturer Part Number

AN2826

Description

DDR-SDRAM Layout Considerations for MCF547x/8x Processors

Manufacturer

Freescale Semiconductor / Motorola

Datasheet

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All memory devices of a single chip select block must have the same configuration and row/column

address width; however, this is not necessary between different blocks. If mixing different memory

organizations in different blocks, the following guidelines will ensure that every block is fully contiguous:

Freescale Semiconductor

128 Mbits

256 Mbits

512 Mbits

64 Mbits

•

Device

If all devices’ row address width is 12 bits, the column address can be greater than or equal to 8

bits.

If all devices’ row address width is 13 bits, the column address can be greater than or equal to 8

bits.

If all devices’ column address width is 8 bits, the row address can be greater than or equal to 11

bits.

x8 and x16 data width memory devices can be mixed (but not in the same space).

512K x 32 bit 11 x 8 x 4

16M x 16 bit

32M x 16 bit

4M x 16 bit

16M x 4 bit

4M x 32 bit

8M x 16 bit

16M x 8 bit

32M x 4 bit

32M x 8 bit

64M x 4 bit

64M x 8bit

Configur

8M x 8bit

ation

DDR-SDRAM Layout Considerations for MCF547x/8x Processors, Rev. 1

12 x 10 x 4

12 x 11 x 4

13 x 10 x 4

12 x 10 x 4

12 x 11 x 4

13 x 10 x 4

12 x 12 x 4

13 x 11 x 4

12 x 11 x 4

12 x 12 x 4

13 x 11 x 4

13 x 10x 4

Row bit x

12 x 8 x 4

12 x 9 x 4

13 x 8 x 4

13 x 9 x 4

12 x 8 x 4

12 x 9 x 4

13 x 8 x 4

13 x 9 x 4

Col bit x

Banks

Table 1. SDRAM Address Multiplexing

128 MB

256 MB

128 MB

256 MB

16 MB

32 MB

64 MB

16 MB

32 MB

64 MB

Block

Total

8 MB

Size

Setting

[MUX]

SDCR

CA11

CA12

—

CA11

CA9

—

CA9

CA8

CA9

CA8

CA9

CA8

CA9

CA8

CA9

CA8

CA9

CA8

CA9

CA8

CA9

CA8

—

Internal Address

RA12

CA8

—

RA11-0 BA1-0

23–12

DDR SDRAM Overview

11–10

CA7-0

9–2

AN2826 Freescale Semiconductor / Motorola, AN2826 Datasheet - Page 5

AN2826

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