AN2826 Freescale Semiconductor / Motorola, AN2826 Datasheet - Page 2

• Manufacturer Part Number: AN2826
• Description: DDR-SDRAM Layout Considerations for MCF547x/8x Processors
• Manufacturer: Freescale Semiconductor / Motorola

DDR SDRAM Overview
This memory controller module has been through various revisions over the last eight years as DRAM
memory architectures evolved, driven mainly by the requirements of the personal computer (PC) market.
The most recent DRAM controller included on the MCF547x/8x family is a completely new design that
supports the latest DRAM architecture: DDR SDRAM. These DRAM devices utilize a Stub Series
Terminated Logic Version 2 (SSTL_2) means of connection and signalling between the MPU and the DDR
SDRAM as described in JEDEC standard EIA/JESD8-9 (See
DDR SDRAM offers over the previous standard DRAM memory SDR (Single Data Rate) SDRAM, is that
data is clocked on both edges of the synchronous clock that is shared between the MPU and the DDR
SDRAM. The result is a potential doubling of the bandwidth between the MPU and the DDR SDRAM.
As these V4e core ColdFire MPUs (MCF547x/548x families) utilize a full Harvard architecture on-chip,
the extra bus bandwidth offered by the DDR SDRAM can be used to great effect to increase
data/instruction throughput on the MPU. This is true particularly when processing blocks of data to/from
some of the high speed peripheral modules on-chip (i.e., the PCI V2.2 bus controller, the two 10/100baseT
Fast ethernet controllers and the one USB 2.0 high speed (480 Mbps) device port). The DDR SDRAM
interface on this family of processors always runs at half the core frequency of the processor. For example,
for the 266 MHz MCF547x processor the DDR SDRAM interface will operate at 133 MHz and clock data
twice during every external clock cycle, thus offering a data throughput similar to the internal core buses
running at 266 MHz. This in turn minimizes the performance penalty paid for off-chip accesses when
fetching either code or data from the DDR SDRAM.
To locate any published errata or updates to this document, please refer to the website at
http://www.freescale.com/coldfire.
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The following terminology is used throughout this application note:
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SDRAM block—any group of DRAM memories selected by one of the MCF547x/8x
SD_CS[3:0] signals. The MCF547x/8x can support up to four independent memory blocks. The
base address of each block is programmed in the SDRAM chip select configuration registers
(CSxCFG).
SDRAM bank—an internal partition in an SDRAM device. For example, a 64-Mbit SDRAM
component might be configured as four 512K x 32 banks. Banks are selected through the
SD_BA[1:0] signals.
SDRAM—RAM that operate like asynchronous DRAM, but with a synchronous clock, a
pipelined, multiple-bank architecture, and faster speeds.
Single data rate (SDR) SDRAM—SDRAM that drives/latches data and command information on
the rising edge of the synchronous clock.
DDR SDRAM Overview
DDR-SDRAM Layout Considerations for MCF547x/8x Processors, Rev. 1
Section 5,
“References”). The advantage that
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