AN2826 Freescale Semiconductor / Motorola, AN2826 Datasheet - Page 10

• Manufacturer Part Number: AN2826
• Description: DDR-SDRAM Layout Considerations for MCF547x/8x Processors
• Manufacturer: Freescale Semiconductor / Motorola

MCF547x/8x Validation Board DDR Layout
Figure 6. MCF547x/8x Validation Board Silkscreen
Figure 6
shows a portion of the top silk screen for the MCF5475/5484 validation board that details the
MPU and DDR SDRAM memory module. The bounding box just below the U5 silkscreen label contains
the SMT (Surface Mount Technology) BGA (Ball Grid Array) footprint for the MPU. J11, J12, J13 and
J16 are SMT logic analyzer connectors for sampling the DDR SDRAM signals that might not be required
in a system design, allowing the DDR SDRAM to be physically closer to the MPU. To the left of the MPU
and beyond these connectors is the DDR SDRAM DIMM (Dual In-line Memory Module) outline. The
outline for this part can be seen next to the pin numbering running up the diagram where 10, 20, 30 etc.
represent the pin numbers on the DDR SDRAM DIMM. These numbers are particularly useful if the
DIMM requires probing with an oscilloscope. The physical positioning of the DDR SDRAM DIMM was
selected so that the control and address/data bus signals associated with the DDR SDRAM from the MPU
had as physically short a path as possible, thus minimizing clock, control, and bus slew in the design. The
area left unpopulated around U5 (MPU) on the top side of the board is deliberate: it allows a BGA socket
to be fitted to test early the MCF5475 and MCF5485 silicon. The components closest to the MPU are the
DDR-SDRAM Layout Considerations for MCF547x/8x Processors, Rev. 1
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Freescale Semiconductor