AN2826 Freescale Semiconductor / Motorola, AN2826 Datasheet - Page 6

• Manufacturer Part Number: AN2826
• Description: DDR-SDRAM Layout Considerations for MCF547x/8x Processors
• Manufacturer: Freescale Semiconductor / Motorola

DDR SDRAM Overview
SDR SDRAM design requires special timing consideration for the SD_DQS[3:0] signals. For reads from
DDR SDRAMs, the memory will drive the SD_DQSx pins so that the data lines and SD_DQSx signals
have concurrent edges. The MCF547x/8x SDRAMC is designed to latch data 1/4 clock after the
SD_DQS[3:0] edge. For DDR SDRAM, this ensures that the latch time is in the middle of the data valid
window. The SDRAMC also uses the SD_DQS[3:0] signals to determine when read data can be latched
for SDR SDRAM; however, SDR memories do not provide SDR_DQS outputs. Instead the SDRAMC
provides an SDR_DQS output that is routed back into the controller as SD_DQS[3:0]. The SDR_DQS
signal should be routed such that the valid data from the SDRAM reaches the MCF547x/8x at the same
time or just before the SDR_DQS reaches the SD_DQS[3:0] inputs. When routing SDR_DQS, the
outbound trace length should be matched to the SDCLK trace length, thus matching the trace length
between the CPU and the SDR SDRAM for the other SDR SDRAM control signals. This will align
SDR_DQS to the SDCLK as if the memory had generated the SD_DQS pulse. The inbound trace should
be routed along the data path. Alternatively, a signal buffer/driver could be inserted to ensure that the
SD_DQS[3:0] signals are all driven correctly, which would in turn add a delay to the initial SD_DQS
signal. This should synchronize the SD_DQS signal so that the data is latched in the middle of the data
valid window as shown below in
DDR DRAM connection is far simpler, as shown in
for routing between the MPU and the DDR SDRAM in
critical to DDR SDRAM operating correctly within a system.
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x32 data width memory devices cannot be mixed with any other width.
MCF547X/8X
DDR-SDRAM Layout Considerations for MCF547x/8x Processors, Rev. 1
Figure 3. MCF547X/8X Connections to SDR SDRAM
SDADDR[12:0]
SDDATA[31:0]
SDCLK[1:0]
SDDQS[3:0]
SDDM[3:0]
SDBA[1:0]
SDRDQS
SDCKE
Figure
SDCSn
SDWE
RAS
CAS
3.
Figure
Section 2.2, “Layout
4; however, please look at the layout guidelines
BA[1:0]
DQM[3:0]
DQ[31:0]
RAS
CAS
CLK
CKE
A[12:0]
CS
WE
Guidelines.” These are
SDR SDRAM
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