AN2826 Freescale Semiconductor / Motorola, AN2826 Datasheet - Page 13

• Manufacturer Part Number: AN2826
• Description: DDR-SDRAM Layout Considerations for MCF547x/8x Processors
• Manufacturer: Freescale Semiconductor / Motorola

MCF547x/8x Validation Board DDR Layout
Figure 8
shows the first of the inner routing layers. The number of tracks on this layer is deliberately kept
to a minimum, as any modifications to this layer would mean drilling the printed circuit board. On all
layers tracks always use 45 degree angles, never 90 degree, to minimize noise in the form of reflections.
Similarly the maximum distance tracks will run in parallel in close proximity is usually less then 2.5 cm
(~1000 mil) if the signals are continuously switching to minimize cross talk noise between tracks.
Figure 9. MCF547x/8x Validation Board Inner2 Layer
Figure 9
shows the second inner routing layer. This second layer shows tracking for the MPU Flexbus
interface (below the MPU), as well as some DDR SDRAM interface routing from above the MPU, towards
some vias which will then route on to the DDR SDRAM DIMM on another layer. For every track between
the MPU and the DDR SDRAM DIMM, the layout tool was used to calculate the point to point distance
of the track. It added the combined track lengths over the various layers on which it is routed. This ensures
signal integrity in terms of skew, as well as the meeting of the target +/- 1.25cm (500mil) on all DDR
SDRAM signal track lengths. Please note the flood-filled area above the MPU; this is a separate power
DDR-SDRAM Layout Considerations for MCF547x/8x Processors, Rev. 1
Freescale Semiconductor
13