CY28347 Cypress Semiconductor, CY28347 Datasheet - Page 9

• Manufacturer Part Number: CY28347
• Description: Universal Single-chip Clock Solution
• Manufacturer: Cypress Semiconductor

Document #: 38-07352 Rev. *C
Maximum Ratings
Input Voltage Relative to V
Input Voltage Relative to V
Storage Temperature: ................................–65 C to + 150 C
Operating Temperature: .................................... 0 C to +70 C
Maximum ESD .............................................................2000V
Maximum Power Supply: ................................................5.5V
DC Parameters
AC Parameters
Parameter
Crystal
TDC
TPeriod
VHIGH
VLOW
Tr / Tf
TCCJ
Txs
Notes:
10. Probes are placed on the pins, and measurements are acquired between 0.4V and 2.4V for 3.3V signals and between 0.4V and 2.0V for 2.5V signals, and
12. When Xin is driven from and external clock source (3.3V parameters apply).
13. When Crystal meets minimum 40 ohm device series resistance specification.
11. Probes are placed on the pins, and measurements are acquired at 2.4V for 3.3V signals and at 2.0V for 2.5V signals.
VIL1
VIH1
VIL2
VIH2
Vol
Iol
Ioz
Idd3.3V
Idd2.5V
Ipd
Ipup
Ipdwn
Cin
Cout
Lpin
Cxtal
3.
4.
5.
6.
7.
8.
9.
Parameter
Multiple Supplies: The Voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
All outputs loaded as per maximum capacitative load table in P4 and DDR mode. See Table 11.
All outputs loaded as per loading specified in the loading table. See Table 11.
This measurement is applicable with Spread ON or spread OFF.
This is required for the duty cycle on the REF clock out to be as specified. The device will operate reliably with input duty cycles up to 30/70 but the REF clock
duty cycle will not be within data sheet specifications.
The typical value of VX is expected to be 0.5*VDDD (or 0.5*VDDC for CPUCS signals) and will track the variations in the DC level of the same.
Measured between 0.2Vdd and 0.7Vdd.
between 20% and 80% for differential signals.
Xin Duty Cycle
Xin Period
Xin HIGH Voltage
Xin LOW Voltage
Xin Rise and Fall Times
Xin Cycle to Cycle Jitter
Crystal Start-up Time
Input LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input HIGH Voltage
Output LOW Voltage for Sreset#
Pull-down Current for Sreset#
Three-state Leakage Current
Dynamic Supply Current
Dynamic Supply Current
Power-down Supply current
Internal Pull-up Device Current
Internal Pull-down Device Current
Input Pin Capacitance
Output Pin Capacitance
Pin Inductance
Crystal Pin Capacitance
Description
(V
DD
[3]
= V
SS
DDQ
Description
:.............................. V
DDPCI
or AV
= V
DD
0.7V
DDAGP
69.84
: ............. V
Min.
45
0
66 MHz
DD
= V
0.3V
Max.
71.0
10.0
V
DDR
500
55
30
DD
DD
SS
DD
= V
+ 0.3V
– 0.3V
Applicable to PD#, F S(0:4)
Applicable to SDATA and SCLK
IOL
VOL = 0.4V
CPU frequency set at 133.3
CPU frequency set at 133.3 MHz
PD# = 0
Input @ V
Input @ V
Measured from the X
0.7V
DD48M
69.84
Min.
45
0
100 MHz
DD
= V
SS
DD
0.3V
This device contains circuitry to protect the inputs against
damage due to HIGH static voltages or electric field. However,
precautions should be take to avoid application of any voltage
higher than the maximum rated voltages to this circuit. For
proper operation, V
range.
V
Unused inputs must always be tied to an appropriate logic
voltage level (either V
Max.
71.0
10.0
DDC
V
500
55
30
SS
DD
Conditions
DD
< (V
= 3.3V ± 5%, V
0.7V
69.84
IN
Min.
IN
45
0
133 MHz
or V
or X
DD
OUT
OUT
[4]
0.3V
Max.
71.0
V
500
55
10
30
) < V
IN
DDI
DD
to V
DD
[4]
SS
and V
= V
DD
SS
or V
0.7V
69.84
DD
Min.
45
OUT
0
200 MHz
DD
= 2.5 ± 5%, T
DD
).
Min.
should be constrained to the
2.0
2.2
0.4
24
27
0.3V
Max.
71.0
V
500
55
10
30
DD
DD
Typ.
156
177
3.8
35
36
Unit
A
ms 9
ns 5,6,7,8
ns 7
ps 10,11,12,13
% 5,6,7,8
V 7,9
V
= 0 °C to +70 °C)
CY28347
Max.
Page 9 of 22
180
200
–25
1.0
1.0
4.0
10
10
45
5
6
7
Notes
Unit
Vdc
Vdc
Vdc
Vdc
mA
mA
mA
mA
pF
pF
pF
pF
V
A
A
A